[GUEST ACCESS MODE: Data is scrambled or limited to provide examples. Make requests using your API key to unlock full data. Check https://lunarcrush.ai/auth for authentication information.]  Jukan [@Jukanlosreve](/creator/twitter/Jukanlosreve) on x 22.5K followers Created: 2025-07-16 06:42:03 UTC Nomura: TSMC CoPoS Delay to 2029-2030 Expected... Could Impact NVIDIA Regarding the AI industry supply chain, Nomura analyzed that TSMC might shift its 2026 backend capital expenditure to other technologies like WMCM (Wafer-level Multi-Chip Module) and SoIC (System-on-Integrated-Chip), and that CoWoS capacity allocation will be a key monitoring point. Significant Delay in CoPoS Technology, NVIDIA Product Roadmap Adjustment Inevitable According to the report, CoPoS technology is designed to support AI GPU demand from customers like NVIDIA by increasing area utilization through larger panel sizes (e.g., 310x310mm). However, Nomura's industry survey indicates a significant slowdown in the development of TSMC's chip-on-panel-on-substrate (CoPoS) packaging technology. The mass production timeline, originally planned for 2027, could be delayed to the second half of 2029. This delay is primarily due to technical immaturity, particularly in addressing key challenges such as managing differences between panels and wafers, controlling warping over larger areas, and handling more redistribution layers (RDLs). The CoPoS delay will directly impact NVIDIA's product planning. Nomura expects that NVIDIA's Rubin Ultra GPU was originally anticipated to require up to eight wafer-sized CoWoS-L interconnects to integrate all chips and chiplet stacks. However, the CoPoS delay might force NVIDIA to switch to an MCM architecture, distributing four Rubin GPUs across two modules connected via a substrate. This adjustment is similar to Amazon AWS's Trainium 2, which uses CoWoS-R and MCM to place compute chips and HBM on an organic interposer, which is then placed on a single substrate. Nomura Securities believes such changes could help NVIDIA circumvent delays but might also increase design complexity and cost. TSMC Faces Capital Expenditure Allocation Adjustment In terms of capacity, Nomura maintained its forecast for TSMC's CoWoS capacity, expecting to reach monthly wafer capacities of XXXXXX in late 2025 and 90,000-100,000 in late 2026. At a monthly wafer capacity level of 100,000, the report expects TSMC not to pre-purchase additional CoWoS capacity equipment, but it might achieve limited capacity growth by improving production efficiency. With the CoPoS mass production delay, TSMC's 2026 backend capital expenditure (which usually accounts for XX% of the total budget) might be more heavily invested in WMCM (Wafer-level Multi-Chip Module) and SoIC (System-on-Integrated-Chip) technologies. The report warned that market expectations for WMCM might be overly optimistic, while expectations for SoIC are relatively conservative. $TSM XXXXXX engagements  **Related Topics** [module](/topic/module) [coins ai](/topic/coins-ai) [$8604t](/topic/$8604t) [$nvda](/topic/$nvda) [stocks technology](/topic/stocks-technology) [Post Link](https://x.com/Jukanlosreve/status/1945373347241714124)
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Jukan @Jukanlosreve on x 22.5K followers
Created: 2025-07-16 06:42:03 UTC
Nomura: TSMC CoPoS Delay to 2029-2030 Expected... Could Impact NVIDIA
Regarding the AI industry supply chain, Nomura analyzed that TSMC might shift its 2026 backend capital expenditure to other technologies like WMCM (Wafer-level Multi-Chip Module) and SoIC (System-on-Integrated-Chip), and that CoWoS capacity allocation will be a key monitoring point.
Significant Delay in CoPoS Technology, NVIDIA Product Roadmap Adjustment Inevitable
According to the report, CoPoS technology is designed to support AI GPU demand from customers like NVIDIA by increasing area utilization through larger panel sizes (e.g., 310x310mm).
However, Nomura's industry survey indicates a significant slowdown in the development of TSMC's chip-on-panel-on-substrate (CoPoS) packaging technology. The mass production timeline, originally planned for 2027, could be delayed to the second half of 2029. This delay is primarily due to technical immaturity, particularly in addressing key challenges such as managing differences between panels and wafers, controlling warping over larger areas, and handling more redistribution layers (RDLs). The CoPoS delay will directly impact NVIDIA's product planning.
Nomura expects that NVIDIA's Rubin Ultra GPU was originally anticipated to require up to eight wafer-sized CoWoS-L interconnects to integrate all chips and chiplet stacks. However, the CoPoS delay might force NVIDIA to switch to an MCM architecture, distributing four Rubin GPUs across two modules connected via a substrate.
This adjustment is similar to Amazon AWS's Trainium 2, which uses CoWoS-R and MCM to place compute chips and HBM on an organic interposer, which is then placed on a single substrate. Nomura Securities believes such changes could help NVIDIA circumvent delays but might also increase design complexity and cost.
TSMC Faces Capital Expenditure Allocation Adjustment
In terms of capacity, Nomura maintained its forecast for TSMC's CoWoS capacity, expecting to reach monthly wafer capacities of XXXXXX in late 2025 and 90,000-100,000 in late 2026. At a monthly wafer capacity level of 100,000, the report expects TSMC not to pre-purchase additional CoWoS capacity equipment, but it might achieve limited capacity growth by improving production efficiency. With the CoPoS mass production delay, TSMC's 2026 backend capital expenditure (which usually accounts for XX% of the total budget) might be more heavily invested in WMCM (Wafer-level Multi-Chip Module) and SoIC (System-on-Integrated-Chip) technologies. The report warned that market expectations for WMCM might be overly optimistic, while expectations for SoIC are relatively conservative.
$TSM
XXXXXX engagements
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