#  @cadencedesignsystems Cadence Design Systems Cadence Design Systems posts on YouTube about systems, design, ai, what is the most. They currently have [------] followers and [---] posts still getting attention that total [-----] engagements in the last [--] hours. ### Engagements: [-----] [#](/creator/youtube::UC5qqAsDzbA0zAQNBBQVsS0Q/interactions)  - [--] Week [------] +1.60% - [--] Month [------] +65% - [--] Months [------] -69% - [--] Year [-------] +133% ### Mentions: [--] [#](/creator/youtube::UC5qqAsDzbA0zAQNBBQVsS0Q/posts_active)  - [--] Week [--] +25% - [--] Month [---] +1.90% - [--] Months [---] +7.10% - [--] Year [---] +63% ### Followers: [------] [#](/creator/youtube::UC5qqAsDzbA0zAQNBBQVsS0Q/followers)  - [--] Week [------] no change - [--] Month [------] +0.74% - [--] Months [------] +4.10% - [--] Year [------] +12% ### CreatorRank: [---------] [#](/creator/youtube::UC5qqAsDzbA0zAQNBBQVsS0Q/influencer_rank)  ### Social Influence **Social category influence** [stocks](/list/stocks) [technology brands](/list/technology-brands) [finance](/list/finance) [events](/list/events) [countries](/list/countries) [automotive brands](/list/automotive-brands) [travel destinations](/list/travel-destinations) [social networks](/list/social-networks) [currencies](/list/currencies) [formula 1](/list/formula-1) **Social topic influence** [systems](/topic/systems), [design](/topic/design), [ai](/topic/ai), [what is](/topic/what-is), [shorts](/topic/shorts), [ip](/topic/ip), [tools](/topic/tools), [flow](/topic/flow), [in the](/topic/in-the), [cadence](/topic/cadence) **Top accounts mentioned or mentioned by** [@cadence](/creator/undefined) [@cadencecom](/creator/undefined) [@nvidia](/creator/undefined) [@samsung](/creator/undefined) [@intel](/creator/undefined) [@thesee](/creator/undefined) [@danfoss](/creator/undefined) [@sumitomoelectric](/creator/undefined) [@voxelsensors](/creator/undefined) [@144gbps](/creator/undefined) [@qciquantumcomputinginc](/creator/undefined) [@baylor](/creator/undefined) [@globalfoundries](/creator/undefined) [@zfgroup](/creator/undefined) [@anirudh](/creator/undefined) [@vlsidcon](/creator/undefined) [@carnamavlogs](/creator/undefined) **Top assets mentioned** [GlobalFoundries (GFS)](/topic/globalfoundries) ### Top Social Posts Top posts by engagements in the last [--] hours "State Space Decoded: How SimAI Optimizes Random Testbenches for Faster Coverage Random testbenches are powerful but without intelligent constraint management they can hide bugs and delay coverage closure. In this episode of Espresso & Electronics we explore how Cadence Xcelium SimAI Exploration Solver transforms verification by analyzing state space identifying coverage holes and guiding randomization toward under-tested regions. Learn why traditional constraint tweaking often leads to over-constrained or under-constrained testbenches and how SimAI helps achieve faster coverage closure" [YouTube Link](https://youtube.com/watch?v=Xm2iohV3pqQ) 2025-11-12T03:45Z 40.7K followers, [---] engagements "Conquer Coverage Gaps with Verisium SimAI Elevate Your Software Game" Learn how shifting left in your testing process can uncover those elusive bugs that traditional methods might miss. We delve into how machine learning is transforming software simulation and verification targeting coverage holes rare failures and streamlining regression compression to ensure bug-free designs faster and more efficiently. Whether you're a developer or a verification engineer this episode provides practical insights into the evolving strategies for ensuring software reliability. If you missed the webinar on" [YouTube Link](https://youtube.com/watch?v=D5XHzp9wGv4) 2024-07-09T17:18Z 40.7K followers, [---] engagements "Using the Cadence VirtualBridge Emulator with the Palladium Platform Narenda Konda Director of Hardware Engineering at Nvidia talks about how the Cadence VirtualBridge Emulator streamlines their emulation flow allowing them to extract more ROI from their investment in emulation technology. Cadence Cadence Design Systems Nvidia Narendra Konda Emulation VirtualBridge Emulator Palladium Palladium Z1 EDA EDA Tools Cadence Cadence Design Systems Nvidia Narendra Konda Emulation VirtualBridge Emulator Palladium Palladium Z1 EDA EDA Tools" [YouTube Link](https://youtube.com/watch?v=MwnGGduhBN4) 2017-04-21T18:54Z 40.7K followers, [----] engagements "STMicroelectronics New flow for analog top level design CDNLive EMEA [----] had several customer experts present innovative tool and design flows to attendees. Watch as Elena Raciti from STMicroelectronics explains how her team used Virtuoso ADE Product Suite in a new flow for analog top level design and went from a manual project management flow to a fully automated design flow. STMicroelectronics Cadence Cadence Design Systems EDA EDA Tools Virtuoso Virtuoso ADE CDNLive CDNLive EMEA CDNLive [----] STMicroelectronics Cadence Cadence Design Systems EDA EDA Tools Virtuoso Virtuoso ADE CDNLive" [YouTube Link](https://youtube.com/watch?v=PKrOQWotZFQ) 2017-06-13T22:25Z 40.7K followers, [---] engagements "Arm and Cadence Showcase AI System Collaboration at AI Infra Summit [----] At AI Infra Summit [----] Arm and Cadence spotlight a transformative partnership shaping the future of AI infrastructure. As workloads scale beyond traditional paradigms the industry is shifting from commodity servers to custom-built silicon and this collaboration is leading the charge. Key discussion points : [--]. Arm Neoverse compute subsystems integrated with Cadence IP : HBM4 for AI training LP6 for inference PCIe Gen7 for cluster scaling and UCIe64 for chiplet integration [--]. Early validation with Palladium Z3 emulation" [YouTube Link](https://youtube.com/watch?v=SIoNpEw__00) 2025-10-28T22:36Z 40.7K followers, [---] engagements "Cadence solutions for the latest PCIe [---] and [---] specifications Preview our solutions for PCIe [---] and [---] at the PCI-SIG Developers Conference encompassing PHY and Controller IP Verification IP and Accelerated VIP/Emulation. Future-proof your designs with our industry leading high performance low power offerings . For more information visit us at https://www.cadence.com/en_US/home/tools/ip/design-ip/discover-pcie5.html Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website:" [YouTube Link](https://youtube.com/watch?v=SkarzQW7IC0) 2021-05-24T22:33Z 40.7K followers, [----] engagements "Keep up with the revolutionCadence Cerebrus Intelligent Chip Explorer Training To meet increased demands of our increasingly connected world semiconductor chips need to be designed faster smaller and smarter. Cadence Cerebrus is a revolutionary and game-changing chip optimization solution enabling this. Join Cadences Cerebrus Intelligent Chip Explorer Training and learn how to use Cadence Cerebrus to scale and automate your design improve your productivity and much more The Online class is free for all Cadence customers with a Learning and Support account. Check out the course details:" [YouTube Link](https://youtube.com/watch?v=WZsxr-Zrp9U) 2023-07-24T13:52Z 40.7K followers, [---] engagements "Cadence Reality DC for Enterprise Data Centers Explore how enterprise data center teams use Cadence Reality DC to assess and manage deployments virtually before implementation in their data center digital twin. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader" [YouTube Link](https://youtube.com/watch?v=n_SCScWVYP8) 2024-03-18T22:00Z 40.7K followers, [---] engagements "Cadence Ranked #36 on Peoples Companies That Care List Cadence is proud to be recognized as #36 on Peoples Companies That Care list This achievement reflects our commitment to fostering a culture of care innovation and collaboration. At Cadence we empower the worlds most innovative companies to design extraordinary products from chips to boards to complete systems for dynamic markets like hyperscale computing 5G communications automotive mobile aerospace consumer electronics industrial and healthcare. Our Intelligent System Design strategy combines cutting-edge software hardware and IP to" [YouTube Link](https://youtube.com/watch?v=00vj7UfP-Gc) 2025-09-09T18:14Z 40.7K followers, [---] engagements "Cadence RTL-to-GDSII Flow Training Your Gateway to Digital Design Traditional design flows can be slow and fragmented. Todays engineers need faster smarter ways to learn and execute. The Cadence RTL-to-GDSII Flow Training Course is your gateway to mastering the complete ASIC design journey from RTL coding to GDSII output in just [--] hours. Why take this course [--]. Learn end-to-end digital design flow [--]. Hands-on experience with seven Cadence tools [--]. Adaptive learning with interactive quizzes [--]. Accelerated training with pre-quiz skip option What youll cover : RTL coding in VHDL or Verilog" [YouTube Link](https://youtube.com/watch?v=2622of0uBPg) 2025-10-07T19:47Z 40.7K followers, [---] engagements "From Design to Operations: Thse Data Centers Digital Twin Transformation with HPE and Cadence Thse Data Center a Tier [--] certified colocation provider near Paris has redefined how data centers are designed and operated. This video explores how Cadence Reality DC Digital Twin and HPE enabled a state-of-the-art facility with six halls optimized for mixed and high-density server hosting. Key highlights : Digital twin for design validation: Prevent hotspots optimize cooling and validate high-density rack layouts Physics-based CFD thermal modeling: Predict outcomes under normal and failover" [YouTube Link](https://youtube.com/watch?v=2Cakv4FVwXI) 2025-10-24T19:59Z 40.7K followers, [---] engagements "Cadence 224G-LR PHY Transmitter Performance Cadences 224G-LR PHY IP is designed for next-generation 800G and 1.6T networks powering AI factories hyperscale data centers and scale-up/scale-out architectures. This video demonstrates transmitter (TX) performance at 212.5Gbps showcasing wide-open PAM4 eyes error-free operation and compliance with industry standards. Key highlights include : PHY IP versatility: Supports long-reach (LR) and short-reach (SR) channels Data rate range: 1.25Gbps to 225Gbps for Ethernet Ultra Ethernet and CXL Advanced DSP and SerDes integration for signal integrity and" [YouTube Link](https://youtube.com/watch?v=6t-22g05-4I) 2025-07-18T20:56Z 40.7K followers, [----] engagements "The Hidden Role of Lock-Up Latches in Semiconductor Chip Design Unlock the secret to flawless multi-clock designs. Discover how Lock-Up Latches eliminate timing violations in your scan chains for 100% data integrity. In the high-stakes world of Intelligent System Design the path from a netlist to a working chip is fraught with timing hazards. While functional operation usually takes center stage the Design for Test (DFT) phase introduces its own unique set of challenges. This is where the Lock-Up Latch steps in. As a specialized sequential element it is strategically inserted into the scan" [YouTube Link](https://youtube.com/watch?v=8rauOf87tF0) 2026-02-09T13:00Z 40.8K followers, [---] engagements "Lip-Bu Tan & Anirudh Devgan on AI Foundry Leadership & Semiconductor Innovation Join @Intel CEO Lip-Bu Tan and @cadencedesignsystems CEO Anirudh Devgan in this exclusive fireside chat at #CadenceLIVE [----] where they share transformative insights on AI strategy semiconductor innovation and engineering culture. Discover how Intel is redefining its approach to agentic AI physical AI and purpose-built silicon while Cadence accelerates design with EDA SDA and advanced tools like Palladium and Millennium. Explore the future of foundry services advanced packaging and system-level design and learn" [YouTube Link](https://youtube.com/watch?v=9tsuXcQOoaE) 2025-05-14T04:25Z 40.7K followers, [----] engagements "What Is Shift Left Vulnerability In this 2.3-minute video you will learn how the ShiftLeft approach is transforming security and verification in modern electronic design. By moving security analysis earlier in the design cycle engineers can proactively detect and resolve vulnerabilities long before fabrication. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/" [YouTube Link](https://youtube.com/watch?v=AIjirFXYCy4) 2026-02-12T05:17Z 40.8K followers, [--] engagements "Whiteboard Wednesday - Introduction to ADAS with a Real-Life Example In this weeks Whiteboard Wednesday Marc Greenberg walks us through a typical ADAS system architecture and then provides a real-life testimonial on the value of these systems. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence" [YouTube Link](https://youtube.com/watch?v=EQL4jeD25_g) 2018-06-20T16:54Z 40.7K followers, 45.4K engagements "Cadence ChipStack AI Super Agent Demo -------------------------------------------------------------------------------------------------------------------------------------- Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About Cadence" [YouTube Link](https://youtube.com/watch?v=FoZb1nL1Iy0) 2026-02-10T16:13Z 40.8K followers, [---] engagements "Cadence CEO Anirudh Devgan Reveals AI Breakthroughs on Mad Money with Jim Cramer AI is reshaping industries and Cadence Design Systems is at the forefront. In this exclusive Mad Money interview CEO Anirudh Devgan shares how Cadence is driving breakthroughs with the Millennium M2000 AI Supercomputer powered by NVIDIA Blackwell technology enabling digital twins for chip design 3D IC automotive aerospace and even drug discovery. Learn how Cadence combines AI-driven design automation with its recurring software business model delivering 80x faster performance and 20x lower power for next-gen" [YouTube Link](https://youtube.com/watch?v=JQ4yGNC_Rqs) 2025-05-21T17:25Z 40.7K followers, [----] engagements "Semiconductor [---] Have you ever wondered about those chips inside your smartphone How are they designed and manufactured Cadences Paul McLellan walks you through how chips get from an idea to a completed design and how the manufacturing process turns sand into valuable electronics. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:" [YouTube Link](https://youtube.com/watch?v=LIuXT6062Ws) 2022-08-24T18:12Z 40.7K followers, 19K engagements "Computational fluid dynamics (CFD) and thermal management Cadence CFD and thermal solutions Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live work and play." [YouTube Link](https://youtube.com/watch?v=QluC9QTpUDA) 2022-06-23T15:14Z 40.7K followers, [---] engagements "Top Five Reasons why you Should Consider a Career as an Application Engineer Discover the top five reasons why you should consider a career as an application engineer at Cadence in this informative video featuring Laya Valsaraj Principal Application Engineer. With over [--] years of experience Laya shares valuable insights into the responsibilities and benefits of this role. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook:" [YouTube Link](https://youtube.com/watch?v=Qm0FCpdijHU) 2023-05-30T14:25Z 40.7K followers, [----] engagements "Employee Spotlight: Amit Sharma At Cadence the Application Engineer role is something where you have a vast horizon to explore and you have the opportunity to work on end-to-end flow. - Amit Sharma Sr. Principal Application Engineer Cadence. Watch this short video to know Amits favourite part about working with Cadence and what he enjoys most about his job. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign" [YouTube Link](https://youtube.com/watch?v=UdyYES35fVo) 2023-05-30T14:17Z 40.7K followers, [----] engagements "Designing an automotive graphics display controller with Stratus HLS In this Expert Insights Video Socionexts Tim Papenfuss discusses how and why they used SystemC and Stratus high-level synthesis (HLS) to design their SC1701 automotive graphics display controller. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:" [YouTube Link](https://youtube.com/watch?v=WWAdZxJE4VI) 2018-11-14T19:52Z 40.7K followers, [---] engagements "Anirudh Devgan and Jensen Huang - CadenceLIVE Silicon Valley [----] - Fireside Chat Hear from Jensen Huang at #CadenceLIVE as he discusses the pivotal role of #AI and accelerated computing in shaping industry mega-trends and how #Nvidia and #Cadence are collaborating to drive transformational change across EDA SDA digital biology and AI. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn:" [YouTube Link](https://youtube.com/watch?v=YUrlLq2CuGM) 2024-04-19T15:07Z 40.7K followers, 37.3K engagements "Static vs Dynamic EM Extraction in AWR Microwave Office Information about Static vs Dynamic EM Extraction in AWR Microwave Office. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon more than [--] years of computational" [YouTube Link](https://youtube.com/watch?v=YUwi4N2Y-uU) 2024-06-06T17:38Z 40.7K followers, [---] engagements "Cadence AI: Transforming the World of Electronic Systems with AI From AI-driven IC and SoC design AI-powered verification and AI-guided PCB design to AI-based multiphysics analysis and AI in digital biology Cadence is harnessing the power of AI to usher in a new era of on-device AI IP and next-generation AI chip creation. In this video learn about the incredible connection between cutting-edge AI chip development and the tangible products that exist all around us. From code to cradle and simulation to satellites AI chips are the driving force behind the technology you rely on every day." [YouTube Link](https://youtube.com/watch?v=_tgEPPWaeI4) 2023-10-02T18:54Z 40.7K followers, [----] engagements "Chip-2-System Power Signoff Part 3: Voltus and Celsius Integration The Chip-2-System Power Signoff video series shows how Voltus IC Power Integrity Solution integrates with key Cadence products to achieve faster system-level power integrity analysis and closure. The third part in this series presents a high-level overview of Voltus IC Power Integrity Solution integration with Celsius Thermal Solver for analyzing the complex interactions between electrical and thermal responses across chip package board and chassis. #LearnWithCadence #EDA #voltus Find more great content from Cadence: Subscribe" [YouTube Link](https://youtube.com/watch?v=jFNBKPIPELs) 2022-12-06T16:24Z 40.7K followers, [----] engagements "3D-IC design analysis and implementation - Cadence Integrity 3D-IC platform Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live work and play. Cadence" [YouTube Link](https://youtube.com/watch?v=lQHNducx3do) 2022-06-23T15:25Z 40.7K followers, [----] engagements "Employee Spotlight: Steven Hollands from the Cadence Cork office Meet Steven Hollands Software Engineering Group Director from our Cork office. In this #EmployeeSpotlight video Steven speaks about what makes him proud to work at Cadence. For six years in a row Cadence has been recognized as a best place to work in Ireland. Come join our team and make your mark Check out our latest job openings - https://bit.ly/cdnsireland #BestWorkplaces #CadenceDesignSystems #GPTW #Hiring Find more great content from Cadence: Subscribe to our YouTube channel:" [YouTube Link](https://youtube.com/watch?v=lvYBWa3ZTWA) 2021-08-11T13:26Z 40.7K followers, [---] engagements "How to Simulate Chiplets 3x Faster with Xcelium Chiplet-based multidie SoCs promise better yield scalability and timetomarket but they also introduce tough verification challenges : variant explosion testbench maintenance interdie interface coverage and endtoend data integrity. In this Cadence Whiteboard session host Aneka Sunanda welcomes Sunil Kashid (Director Samsung SSIR) to break down where to start with multidie verification how to handle homogeneous vs. heterogeneous splits and how Cadence Xcelium Distributed Simulation App helps teams run multidie simulations up to [--] faster while" [YouTube Link](https://youtube.com/watch?v=oGPkiFqbfwc) 2025-09-23T17:56Z 40.7K followers, [---] engagements "Conformal AI Studio AI-Powered ECO & Low Power Signoff Cadence Conformal AI Studio introduces AI and ML to revolutionize SoC verification. Built on decades of trusted Conformal technology this next-gen platform delivers : ✔ AI dashboards & ML-driven proof engines for logical equivalence checking ✔ Automated functional ECO generation for efficient implementable patches ✔ Low-power signoff for complex SoCs with hierarchical flows Core Products : ✔ Conformal AI Equivalence: Distributed Boolean equivalence tracking with AI insights ✔ Conformal AI ECO: Pre/post-mask ECO automation for predictable" [YouTube Link](https://youtube.com/watch?v=oSXC8fznDz0) 2025-03-13T14:30Z 40.7K followers, [---] engagements "Cadence Neo NPU Scalable AI IP with Industry-Leading TOPS per Watt Discover Cadence Neo NPU: a scalable AI acceleration IP ranging from [---] to [--] TOPS with industry-leading TOPS per watt and 2D/3D data engines. This technical spotlight is designed for SoC Architects and AI Hardware Engineers who need to balance extreme performance with a strict power envelope. As Edge AI shifts toward [----] standards selecting an IP that offers high TOPS per watt is essential for thermal management in mobile automotive and IoT devices. The Evolution of AI Acceleration IP At CES [----] Cadence introduced a new" [YouTube Link](https://youtube.com/watch?v=otRtXg2wrtQ) 2025-02-13T18:15Z 40.7K followers, [---] engagements "My Life at Cadence: Madhuparna Datta This short video introduces Cadences Madhuparna Datta from the UK Cadence office. She explains why she became an engineer and what makes her to enjoy working at Cadence. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and" [YouTube Link](https://youtube.com/watch?v=pxWD17cn3TU) 2021-06-16T18:35Z 40.7K followers, [----] engagements "Super Bowl Spirit & Community Impact: Cadence City Year & Kidango Unite Cadence volunteers rolled up their sleeves and joined over [---] community volunteers for the City Year Bay Area and Kidango "Every Student Deserves a Coach" Service Day. Together volunteers painted a vibrant mural in East Palo Alto transforming spaces that spark creativity and build community pride for local students. As Super Bowl excitement builds at Levi's Stadium in Santa Clara we're proud to keep the spirit of teamwork and impact alive in our own backyard. This is what community is all aboutshowing up collaborating" [YouTube Link](https://youtube.com/watch?v=reQGDhuCjkg) 2026-02-10T19:05Z 40.8K followers, [--] engagements "Jensen Huang & Anirudh Devgan on AI Factories Digital Twins & Future of Design Automation Join #NVIDIA CEO Jensen Huang and #Cadence CEO Anirudh Devgan in an exclusive fireside chat at CadenceLIVE [----] where they unveil the future of AI-driven design automation digital twins and accelerated computing. This conversation explores how agentic AI systems physical AI and AI factories will transform industries from semiconductor design to robotics and life sciences. Discover how Cadence Palladium and the groundbreaking Millennium M2000 platform powered by NVIDIA Blackwell architecture are" [YouTube Link](https://youtube.com/watch?v=tbdnk0VfoKQ) 2025-05-14T22:09Z 40.7K followers, 10.4K engagements "Wiwynn Provides Energy-Optimized Data Center IT Solutions from Cloud to Edge with Cadence Optimality In the AI era as the signal-data rate is increasing the signal integrity challenges in server designs are also increasing. Wiwynn is committed to providing hyperscale data centers with innovative cloud IT infrastructure. Their mission is to bring the best total cost of ownership (TCO) energy and energy-itemized IT solutions from the cloud to the edge. Learn more about how Wiwynn is developing a new methodology for PCB designs with Cadences Optimality Intelligent System Explorer and Clarity 3D" [YouTube Link](https://youtube.com/watch?v=tsGYrmsjNCY) 2024-02-20T19:39Z 40.7K followers, [----] engagements "How Hardware Accurate Manufacturing Correlated Digital Twin Process Works This video explains how hardware-accurate manufacturing correlated digital twin process works. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About Cadence :" [YouTube Link](https://youtube.com/watch?v=u4oEuhV2d7Y) 2026-02-12T05:15Z 40.8K followers, [--] engagements "What is the Antenna Effect in VLSI Design #cadence #electricalengineering #computereducation The antenna effect is a critical challenge in VLSI physical design impacting chip reliability and yield during semiconductor manufacturing. In this video we explain what the antenna effect is why it occurs and how designers mitigate its risks using antenna rules and diodes. During fabrication steps like plasma etching long metal interconnects can accumulate charge acting like antennas. If this charge discharges into the gate oxide of transistors before they are connected to power or ground it can" [YouTube Link](https://youtube.com/watch?v=2htO89xz16M) 2026-02-12T10:00Z 40.8K followers, [---] engagements "High-speed ECU design and analysis Cadence Allegro PCB Design Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live work and play. Cadence software hardware and" [YouTube Link](https://youtube.com/watch?v=5xVl3sEhKuI) 2022-06-23T15:17Z 40.7K followers, [---] engagements "What Is a Digital Twin In this 1.3-minute video you will have a quick introduction to digital twinsvirtual models that mirror realworld objects or systems for realtime simulation accurate behavior modeling and continuous monitoring across chip system and RF domains. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/" [YouTube Link](https://youtube.com/watch?v=8tmcdwpWm9Y) 2026-02-12T05:19Z 40.8K followers, [--] engagements "Introduction to Cadence Cloud Learn more about the Cadence-Managed Cloud and Customer-Managed Cloud offerings and benefits. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming" [YouTube Link](https://youtube.com/watch?v=DYhuWXUZXEw) 2023-04-18T21:23Z 40.7K followers, [---] engagements "Cadence CXL VIP Features Explore the features of Cadence Verification IP (VIP) for Compute Express Link (CXL). Learn how this IP verifies CXL.io CXL.cache and CXL.mem semantics across CXL [---] [---] and 3.x standards. Built on Proven PCIe Ecosystem The Cadence CXL VIP leverages the robust architecture of the Cadence PCIe VIP ensuring seamless integration for designs reusing PCIe Physical layers. It supports all critical device configurations: Type 1: CXL.io + CXL.cache (Accelerators) Type 2: CXL.io + CXL.cache + CXL.mem (GPUs/FPGAs) Type 3: CXL.io + CXL.mem (Memory Expanders) Key Capabilities :" [YouTube Link](https://youtube.com/watch?v=EMJmrjwU_74) 2025-12-18T14:32Z 40.7K followers, [--] engagements "The Basics of Design for Testability DFT Rule Checks #automobile #computereducation This asset describes the Basics of Design for Testability (DFT) Rule Checks. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About Cadence : Cadence is" [YouTube Link](https://youtube.com/watch?v=HNevOA-Khy0) 2026-02-09T17:15Z 40.8K followers, [---] engagements "Cadence Enters a New Era with EDA [---] and Cadence JedAI Platform At Cadence we see a great opportunity for our industry to enter a new era of EDA [---] defined by AI-driven platforms that optimize horizontally across multiple runs of many tools throughout an entire system design program. Learn how EDA [---] is bringing all design and verification data together under a unified data platformRTL layouts constraints waveforms coverage reports log files state graphs AI models and metadata with our new Cadence Joint Enterprise Data and AI (JedAI) Platform. Find more great content from Cadence:" [YouTube Link](https://youtube.com/watch?v=HNxe0cd6I_c) 2022-09-13T14:15Z 40.7K followers, [----] engagements "FPGA vs Emulation: What Every ASIC Designer Must Know Before Tapeout. #cadence #eda #pcbdesign In this 1-minute video you will learn the complementary roles of emulation and FPGA prototyping in SoC bring-up. Emulation enables fast deep hardware debugging to ensure RTL correctness while FPGA prototyping delivers the speed needed to validate OS drivers and applications. It also highlights common constraintssuch as FPGA storage limitsand reinforces the rule: dont tapeout until the software is confirmed to work as intended. Connect with Cadence : YouTube:" [YouTube Link](https://youtube.com/watch?v=NbMWREagYVg) 2026-01-28T11:02Z 40.8K followers, [---] engagements "Comparing PDN Simulation to Measurements for AR/VR Products Kundan Chand power integrity engineer Meta Platforms presents a power delivery network (PDN) measurement methodology and correlation exercise compares the simulation results to measurement and discusses the results in one of Signal Integrity Journals Top [--] webinars of [----]. Connect with Cadence: Website: http://www.cadence.com YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:" [YouTube Link](https://youtube.com/watch?v=QSjSAa87C7c) 2023-11-30T04:02Z 40.7K followers, [---] engagements "A Design with Test Circuit #automobile #computereducation #softwarearchitecture This asset is youtube video of a design with test circuit. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About Cadence : Cadence is a global leader in" [YouTube Link](https://youtube.com/watch?v=SF1g8U9F7j4) 2026-02-09T04:00Z 40.8K followers, [----] engagements "EDA Security Deep Dive: Attack Types Tools and Testbench Techniques In this video you will get a quick overview of attack surfaces and vulnerability types in the EDA flow. This training byte breaks down logic digital and analog/mixedsignal attack vectorscovering sequence manipulation sidechannels Trojan insertion fault injection timing/power/thermal exploits and glitch/RFbased attacks. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X:" [YouTube Link](https://youtube.com/watch?v=SaEJdKXqlt4) 2026-02-12T05:14Z 40.8K followers, [--] engagements "How to Fix Asynchronous Set and Reset Pins Violation #automobile #computereducation Fixing Asynchronous Set and Reset Pins Violation Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About Cadence : Cadence is a global leader in" [YouTube Link](https://youtube.com/watch?v=TwCqyyvq-Bs) 2026-02-09T10:00Z 40.8K followers, [----] engagements "Characterizing 22FDX Library at GLOBALFOUNDRIES In this video Ning Jin principal engineer on the Digital Design Methodology Team at GLOBALFOUNDRIES discusses how the company overcame library characterization challenges using Cadence Virtuoso Liberate characterization solution to characterize the library for its 22FDX technology. She also talks about how Cadence Virtuoso Variety helped with statistical characterization of their technology's LVF libraries. Ning discussed library characterization at this year's CDNLive Silicon Valley conference. View her presentation Session CUS202 in the" [YouTube Link](https://youtube.com/watch?v=gSR5dw6Xof8) 2016-05-26T18:21Z 40.7K followers, [----] engagements "Prevent Pre-Silicon Hardware Attacks: How Shift-Left Secures Your Chip Design#softwarearchitecture In this 2.3-minute video you will learn how the ShiftLeft approach is transforming security and verification in modern electronic design. By moving security analysis earlier in the design cycle engineers can proactively detect and resolve vulnerabilities long before fabrication. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence" [YouTube Link](https://youtube.com/watch?v=geI9C02L-9E) 2026-01-23T00:00Z 40.8K followers, [----] engagements "Cadence Debuts Industrys First RealTime eUSB2V2 Demo at CES [----] Powered by 3nm Tech Think USB [---] is slow Think again. Discover how Cadence's brand-new eUSB2V2 IP achieves 10x the speed of legacy standards on a cutting-edge 3nm node. Innovation often means taking something familiar and making it extraordinary. The USB interface standard has been a staple of our digital lives for decades but as we move into the era of Advanced node manufacturing the old ways are no longer enough. Enter eUSB2V2 : a Low voltage USB [---] technology designed to thrive where others struggle. At Cadence we believe" [YouTube Link](https://youtube.com/watch?v=gkZz-8faQBI) 2026-02-04T23:07Z 40.8K followers, [----] engagements "Cadence ChipStack AI Super Agent Demo Overview -------------------------------------------------------------------------------------------------------------------------------------- Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About" [YouTube Link](https://youtube.com/watch?v=p_U-4-jKgcU) 2026-02-10T16:13Z 40.8K followers, [----] engagements "How Sand Converts to Semiconductor Wafer In this video you will discover how ordinary sand transforms into the foundation of modern electronics This video breaks down the semiconductor manufacturing journeyfrom raw silicon extraction and ingot formation to wafer slicing processing polishing and advanced steps like doping lithography etching and EUV patterning. A quick highlevel walkthrough of the [--] essential steps that turn sand into a finished semiconductor wafer. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn:" [YouTube Link](https://youtube.com/watch?v=qzLcoKqUeXo) 2026-02-12T05:18Z 40.8K followers, [--] engagements "Employee Spotlight: Ashwini Kulkarni I was always interested in logical reasoning and problem-solving so I chose electronic engineering as I was fascinated by the whole idea of how small circuits made peoples life easy. - Ashwini Kulkarni Principal Application Engineer Cadence. Watch this short video to know Ashwinis favourite part about working with Cadence and what she enjoys most about her job. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook:" [YouTube Link](https://youtube.com/watch?v=umSfV3IpE50) 2023-05-30T14:17Z 40.7K followers, [----] engagements "Introduction to Cadence-Managed Cloud Service Learn more about the key benefits and features of Managed Cloud Service provided by Cadence for EDA workloads. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end" [YouTube Link](https://youtube.com/watch?v=xe5mizK_KoU) 2023-04-18T21:23Z 40.7K followers, [---] engagements "Quantum Machines Advances Quantum Computing with Cadence AWR Design Platform Quantum computing is unlocking possibilities beyond classical systems from drug discovery and materials research to optimization and cryptography. But building quantum hardware requires precision speed and advanced design tools. In this video Quantum Machines shares how its hybrid control approach powered by the OPX1000 platform eliminates friction between quantum and classical operations enabling real-time feedback error correction and scalable multi-qubit calibration. To achieve this Quantum Machines relies on" [YouTube Link](https://youtube.com/watch?v=0gt1bMIpwz0) 2025-05-21T23:10Z 40.6K followers, [---] engagements "Power Integrity in Chip Design: The Sanity Check You Cant Skip #cadence #eda #pcbdesign The design sanity checks are crucial for power integrity validation and early detection of connectivity issues power vias and timing libraries that can prevent design disasters and ensure robust reliable SoCs. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/" [YouTube Link](https://youtube.com/watch?v=1nXj_d1fJ9k) 2026-01-29T16:15Z 40.8K followers, [---] engagements "Cadence 224G-LR PHY: Receiver Performance Demo for 800G & 1.6T Networks Cadences 224G-LR PHY IP is engineered for next-generation 800G and 1.6T networks enabling AI factories hyperscale data centers and scale-up/scale-out architectures. This video demonstrates receiver (RX) performance showcasing wide-open eyes low BER and advanced diagnostics for high-speed connectivity. Key highlights include : PHY versatility: Supports long-reach (LR) and short-reach (SR) channels Data rate range: 1.25Gbps to 225Gbps for Ethernet Ultra Ethernet and UALink Advanced DSP and SerDes integration for signal" [YouTube Link](https://youtube.com/watch?v=3CXAw_zQ-O4) 2025-07-09T21:04Z 40.6K followers, [---] engagements "How Cadence & @NVIDIA Are Powering the Fourth Industrial Revolution with Palladium Z3 & Protium X3 The Fourth Industrial Revolution is accelerating because we finally have the computational power to push AI from theory into production. For decades artificial intelligence algorithms existed on paper waiting for the hardware to catch up. With modern GPUs placed squarely in computational mode AI is now practical at scale. Consider NVIDIAs Blackwell GPU : a single device with [---] billion transistors. Designing and verifying something this complex both as an isolated processor and inside a broader" [YouTube Link](https://youtube.com/watch?v=3PUd9c5dAI4) 2025-03-11T21:20Z 40.6K followers, [----] engagements "Whiteboard Wednesdays - Introduction to Convolutional Neural Networks (CNN) In this week's Whiteboard Wednesdays video the first in a two-part series Megha Daga explores Convolutional Neural Networks which are biologically inspired models of neurons in the brain. She details how CNN is leveraged in many of today's use cases such as mobile surveillance and automotive" [YouTube Link](https://youtube.com/watch?v=5VuEkubgDiw) 2017-03-22T16:24Z 40.6K followers, 76.7K engagements "Cadence Cerebrus AI Studio: Industrys First Agentic AI Multi-Block Multi-User SoC Design Platform Join Lokesh Korlipara VP of R&D at Cadence as he introduces Cadence Cerebrus AI Studio the industrys first agentic AI-powered multi-block multi-user SoC design platform. Built on advanced AI-driven digital implementation tools this solution accelerates time-to-market by 5X10X enabling engineers to meet aggressive PPA targets while reducing turnaround time. Cerebrus AI Studio combines principled optimization advanced data analytics and AI agents to automate hierarchical design flows. Key features" [YouTube Link](https://youtube.com/watch?v=7SsxlMceWpw) 2025-05-07T17:00Z 40.6K followers, [---] engagements "Or Maltabashi Bar Ilan University Master Thesis Award Recipient Or Maltabashi Bar Ilan University is the recipient of the Cadence Academic Network Master Thesis Award for EDA [----] for his thesis titled "Automatic Guided Physical Implementation of Common Digital Structures." Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:" [YouTube Link](https://youtube.com/watch?v=9wrotePzdKs) 2020-07-23T00:55Z 40.6K followers, [---] engagements "View Cadence Automotive Offerings with the Automotive Innovation Platform Cadence offers numerous products and solutions targeted for automotive applications. The interactive Cadence Automotive Innovation Platform provides short videos that explain the latest automotive innovations in IP system verification functional safety system analysis chiplets/3DIC CFD and thermal. Learn more about each topic by downloading additional resources like white papers or visit our website at https://www.cadence.com/en_US/home/solutions/automotive-solution.html. Connect with Cadence: Website:" [YouTube Link](https://youtube.com/watch?v=ACcf-gU9pKM) 2023-11-28T15:47Z 40.6K followers, 530.1K engagements "Life at Cadence Milan Simon Kmeti on Engineering AI & Recharge Days Meet Simona Cometti Lead Application Engineer at Cadence as she shares why working at Cadence is exciting and rewarding. From a young dynamic environment full of new ideas to opportunities for innovation Simona explains why she never gets bored at work. She also talks about how she uses Cadence Recharge Days to spend quality time with family and friends outside Milan and shares her perspective on Artificial Intelligence (AI) its huge potential and the importance of integrating it into Cadence tools and solutions. Key Topics" [YouTube Link](https://youtube.com/watch?v=AfO7rk5SA3s) 2025-04-15T03:48Z 40.6K followers, [---] engagements "How @Thesee Data Center Uses Cadence Digital Twin for Tier [--] Operations Discover how Thesee Data Center a Tier [--] certified colocation provider near Paris is transforming data center design and operations with Cadence Reality Digital Twin Platform. This video highlights the ecological operational and security benefits of integrating digital twin technology into mission-critical infrastructure. Key advantages include : Energy efficiency optimization and improved PUE (Power Usage Effectiveness) Remote capacity planning and real-time monitoring from anywhere Seamless integration with Building" [YouTube Link](https://youtube.com/watch?v=IhQK_BGlKF4) 2025-09-02T18:24Z 40.6K followers, [---] engagements "Whiteboard Wednesdays Advantages of the MIPI I3C Interface In this week's Whiteboard Wednesdays video Alex Passi explains the advantages provided by the new MIPI I3C interface. With I3C mobile device sensors can transmit data faster with lower power and simpler routing than with existing interfaces" [YouTube Link](https://youtube.com/watch?v=K8LjIEC3UEo) 2016-06-01T17:55Z 40.6K followers, [----] engagements "Cadences Artisan Foundation IP Learn how Cadence Artisan Foundation IP optimizes advanced SOC design through silicon-proven standard cells and SRAM memory compilers to ensure superior PPA targets. The Foundation of Advanced Silicon Design In the competitive landscape of semiconductor manufacturing the Artisan Foundation IP stands as the critical infrastructure for every breakthrough. This suite provides the fundamental building blocks required for complex SOC Design ensuring that your architecture is not only functional but optimized for the most demanding power and performance constraints." [YouTube Link](https://youtube.com/watch?v=MTmREEHIZWk) 2025-12-18T21:14Z 40.6K followers, [---] engagements "AI in RTL-to-GDSII Flow Cadence Webinar on Synthesis & Signoff Ready to accelerate your digital design flow Join Cadence for an exclusive training webinar on the RTL-to-GDSII back-end flow where well explore how AI-driven features simplify synthesis to signoff and boost productivity for physical design engineers. In this 1-hour session Saias Lead Education Application Engineer at Cadence walks you through the latest innovations in tools like Genus Innovus and Tempus covering everything from logic synthesis to timing closure. Whether youre a beginner or refreshing fundamentals this webinar is" [YouTube Link](https://youtube.com/watch?v=RNS6tz_ZglU) 2025-09-23T16:38Z 40.6K followers, [---] engagements "Bar-Ilan University Hackathon hosted at Cadence Petah Tikva Cadence Petah Tikva hosted the annual hackaton of the Faculty of Engineering at Bar-Ilan University on June 8-9 [----]. The Hackathon focused on developing defensive solutions for smart cities applied on existing robotics and drones. [---] students accompanied by [--] mentors faculty and industry partners worked for [--] consecutive hours to address technical and operational challenges and develop advanced solutions with practical feasibility. Find more great content from Cadence: Subscribe to our YouTube channel:" [YouTube Link](https://youtube.com/watch?v=SNmX2r6vGqU) 2023-07-18T22:29Z 40.6K followers, [---] engagements "Explore How Samsung Achieved 11% PPA Gain with Cadence Cerebrus AI Studio Discover how @Samsung Semiconductor India Research (SSIR) is transforming SoC design workflows using Cadence Cerebrus AI Studio. By leveraging this AI-driven multi-user multi-block chip design platform SSIR achieved 811% PPA improvement on SoC subsystems a significant productivity win. Cerebrus AI Studio empowers engineers with customizable dashboards advanced data analytics and Smart Model Replay to accelerate design closure and optimize performance. From congestion analysis to clock tree debugging this collaboration" [YouTube Link](https://youtube.com/watch?v=TLC15lXxgHc) 2025-05-07T17:00Z 40.6K followers, [---] engagements "Joules Power Calculator Training Empower your Power Searching for solutions to power related challenges What if power consumption was accurate and connected and consistent Wouldnt that be ideal The new Cadence Joules RTL Power Solution closes the gapsrevolutionizing traditional power analysis methods and the power efficiency of RTL. Learn all about the unrivaled features of the new Cadence Joules RTL Power Solution by joining the Joules Power Calculator training expedition. Because the better you understand power the better you can optimize it. Check out the course details." [YouTube Link](https://youtube.com/watch?v=VTSnIMEAHbU) 2021-08-10T16:12Z 40.6K followers, [---] engagements "Cadence PCIe VIP Features Verify your next-gen high-speed designs with Cadence PCIe Verification IP (VIP). This video details the complete feature set for PCIe Gen [--] through Gen [---] covering speeds from [---] GT/s to [---] GT/s. Comprehensive Protocol Support : The Cadence PCIe VIP is the industry benchmark for verifying Root Complex Endpoint and Switch designs. It includes full support for: PCIe [---] (128 GT/s): Advanced FLIT formats PAM4 signaling and Forward Error Correction (FEC). NVMe 2.0: Integrated verification for Non-Volatile Memory Express storage protocols. CXL 3.0: Seamless" [YouTube Link](https://youtube.com/watch?v=aOjPCKLSr60) 2025-12-18T14:35Z 40.6K followers, [---] engagements "A Day in the Life of a Lead Application Engineer at Cadence Employee Spotlight Meet Paolo Vernelli Lead Application Engineer at Cadence Milan as he shares what makes Cadence a great place to work. Paolo highlights two key aspects of his experience: Collaboration with Colleagues A supportive team environment that fosters innovation and teamwork. Customer Interaction Direct engagement with customers that creates a dynamic and exciting work culture. Discover how Cadence empowers its employees to thrive in a collaborative setting while working on cutting-edge technologies for global customers." [YouTube Link](https://youtube.com/watch?v=cHbKUAW-kxs) 2025-04-15T03:48Z 40.6K followers, [--] engagements "AI-Driven DSPs for Safer Smarter and Immersive Automotive Experiences Cadence Technologies AIdriven DSP for automotive ADAS and smart cabin sensor fusion incabin sensing and lowlatency audio. This talk shows how Cadence Tensilica DSP cores and Neo (NPU/AI accelerator) power modern vehicles: from external sensing (vision radar lidar thermal) to incabin sensing (driver monitoring child presence detection occupant monitoring) and infotainment (immersive sound ANC beamforming). Youll see how DSPs enable state estimation planning & prediction and control with the latency and power efficiency ADAS" [YouTube Link](https://youtube.com/watch?v=gYhQ5wwsMbo) 2025-03-25T17:44Z 40.6K followers, [---] engagements "Cadence PCIe VIP Complete Feature Overview for PCIe Gen [--] Explore the Cadence PCIe Verification IP (VIP) and its advanced capabilities for verifying PCIe-based designs. This video provides a comprehensive overview of PCIe VIP features supporting PCIe generations [--] through [--] along with related protocols like CXL (1.1 [---] 3.1) CCIX (1.0 [---] 2.0) and NVMe. Cadence PCIe VIP offers : Host device and switch verification across all native and downgraded widths Support for serial and pipe interfaces including NRZ and PAM4 signaling Over [---] timing parameters [----] checkers and [----] configurable" [YouTube Link](https://youtube.com/watch?v=jvvR1FUGN4A) 2025-04-11T11:59Z 40.6K followers, [---] engagements "AI-Powered PCB Design (How @danfoss Uses Cadence Allegro X AI) @danfoss a global leader in energy-efficient technologies is leveraging Cadence Allegro X AI to transform its PCB design flow as part of its LEAP [----] strategy. With a focus on Amplify AI Danfoss aims to speed up placement reduce noise and optimize power integrity for advanced boards powering industrial and sustainable solutions. In this video hear how AI-driven PCB design is helping engineers : [--]. Accelerate initial placement for thousands of components [--]. Improve decoupling capacitor positioning for better signal integrity 3." [YouTube Link](https://youtube.com/watch?v=ljS9pY3dqnU) 2025-09-24T19:02Z 40.6K followers, [---] engagements "The Surprising Industries Behind the Semiconductor Chip Innovations. #cadence #eda #pcbdesign In this 1-minute video you will explore the major endmarket shaping todays semiconductor industry from the massive smartphone ecosystem to advanced automotive systems aerospace innovation hyperscale data centers life sciences and the rapidly expanding IoT world. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram:" [YouTube Link](https://youtube.com/watch?v=m25kjgJWuEI) 2026-01-29T11:10Z 40.8K followers, [---] engagements "IR Drop in VLSI (How It Impacts Timing Clock Skew & Design Performance) IR drop is one of the most critical challenges in chip design and its impact on timing can lead to serious performance issues. In this video we explain how IR drop affects signal nets clock nets and overall design integrity. Youll learn : Why IR drop causes setup time violations and hold time violations How clock skew introduced by IR drop leads to silicon failures The effect of power rail IR drop on weakened drivers increased delays and reduced noise margins Why nominal voltage swing differs from IR drop voltage swing" [YouTube Link](https://youtube.com/watch?v=m9j-2i8gJRM) 2025-11-26T09:52Z 40.6K followers, [---] engagements "Cadence Multi-Protocol PHY Demo: Simultaneous PCIe [---] and 25G Ethernet over a Unified Interface In modern SoCs flexibility isnt optional its essential. This demo showcases Cadence Whistler PHY IP a 32Gbps multi-protocol SerDes solution designed to simplify architectures and accelerate bring-up. Key highlights : Supports PCIe [---] and 25G Ethernet (25G-KR) concurrently over a single PHY Operates from 1.25Gbps to 32Gbps with low latency and long-reach equalization Delivers exceptional power efficiency for high-performance systems Silicon-proven across 7nm to 3nm nodes Why choose Whistler PHY" [YouTube Link](https://youtube.com/watch?v=mqrNCt03cjA) 2025-10-08T19:53Z 40.6K followers, [---] engagements "AI Buildathon Sparks Change at Cadence HQMore Events Coming 🌍 #cadence #eda #ai Our SSG IP EDA and IT teams came together to drive new ideas exemplifying our "One Cadence One Team" spirit and showing the true power of collaboration. Alex Sgouros VP Engineering for Silicon Customer Enablement reflected on the impressive solutions and teamwork displayed throughout the event. He also shared our exciting vision to bring these AI Buildathons to more regionsincluding India China the East Coast Texas and EMEAin the months ahead. Thank you to everyone who participated and made this event" [YouTube Link](https://youtube.com/watch?v=npSfRMtE0xE) 2026-01-29T22:15Z 40.8K followers, [---] engagements "Most Common LVS Errors in Layout and Schematic Here is a quick reference on common issues in schematic and layout related to device extraction during the LVS process. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon" [YouTube Link](https://youtube.com/watch?v=pyZ6n_cWqGY) 2024-12-17T17:17Z 40.6K followers, [---] engagements "FPGA Prototyping Challenges & Trends Cadence Proteum X3 Explained Welcome to Espresso and Electronics your quick sip of EDA wisdom In this episode host Anukica Sunda talks with Lance Tamura Product Management Director at Cadence about the evolving world of FPGA-based prototypinga critical methodology for validating complex SoCs before tape-out. Lance shares why many companies struggle to build their own prototypes the challenges of FPGA prototyping and why enterprise prototyping platforms like Cadence Proteum X3 are transforming the design process. Learn about partitioning complexity timing" [YouTube Link](https://youtube.com/watch?v=qfXUMZIsxJk) 2025-11-12T20:00Z 40.6K followers, [---] engagements "Beginners Guide to How Timing Budgets Improve Hierarchical STA Closure Master hierarchical STA with precise timing budgets. Learn how SDC constraints like set_input_delay and set_load ensure top-level timing convergence. In a modern Intelligent System Design environment monolithic timing analysis is no longer scalable. This video is a designed for STA Engineers and Physical Design Leads who need to decouple block-level implementation from top-level constraints. Without a clear Timing Budget Allocation top-level integration is often plagued by Top-Level Integration Surprises and endless" [YouTube Link](https://youtube.com/watch?v=xS0mDMIjGjY) 2026-01-28T03:56Z 40.8K followers, [---] engagements "How MemryX Powers Edge AI with Cadence Design Tools AI is moving from data centers to edge devices and MemryX is leading the way. This video explores how MemryX tackles the challenges of deploying AI at the edge: achieving cloud-level accuracy overcoming power constraints and delivering high performance without advanced cooling. Learn how MemryXs architecture supports 1000+ models without compression pruning or quantization ensuring what you train is what you infer. Key Highlights : AI at the edge (0:08): Why moving from cloud to edge matters for future applications. Challenges (1:09):" [YouTube Link](https://youtube.com/watch?v=-GSZTS7biuI) 2025-03-25T16:21Z 40.6K followers, [---] engagements "Targeting Critical Nets with NDRs for Robust Timing Closure during VLSI PnR #cadence #pcbdesign #eda Timing closed everywhere except a few stubborn paths Non Default Rules (NDRs) are used for critical nets to reduce delay and improve signal integrity. Use NDRs strategically because they consume additional area and may cause routing congestion. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram:" [YouTube Link](https://youtube.com/watch?v=0E23jtSTC44) 2026-02-06T06:30Z 40.8K followers, [----] engagements "Cadence Community Forums This video is a walk-through on how to access Forums whats in it for a customer and how can the customers take advantage of the Community Recognition Program. #LearnwithCadence #TechnicalForums #CadenceCommunity Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence" [YouTube Link](https://youtube.com/watch?v=0WMIswBOSXc) 2023-08-02T14:10Z 40.7K followers, [---] engagements "What Is Optimization in Digital Implementation (Timing Power & Area Explained) Optimization in digital implementation is the process of iterating through a design to meet multiple objectives : [--]. Timing [--]. Signal integrity (SI) [--]. Power and [--]. Area This video explains what optimization means in the context of physical design flows and why its critical for achieving design closure. Optimization can be broken down into four key areas : [--]. Timing optimization: Ensures paths meet setup and hold requirements [--]. Signal integrity optimization: Reduces noise and crosstalk for reliable operation 3." [YouTube Link](https://youtube.com/watch?v=0hTrwjsFwhw) 2025-08-04T18:35Z 40.6K followers, [---] engagements "Raspberry Pi Uses Cadence to Design Computers for Everybody Learn how Raspberry Pi have used Cadence Allegro X Xcelium verification and digital full flow tools to design from PCB to silicon their enormously popular industrial and educational single-board computers. #raspberrypi #cadencedesignsystems Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/" [YouTube Link](https://youtube.com/watch?v=0nSk3A59oX0) 2021-12-16T05:56Z 40.6K followers, [----] engagements "Reviewing and Validating the Alternative EVS Codec Hear from Stefan Doehla Group Manager and Standards Engineer at Fraunhofer IIS as he discusses the alternative EVS codec. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the" [YouTube Link](https://youtube.com/watch?v=12r5r5KIETw) 2021-05-07T07:00Z 40.6K followers, [---] engagements "Cadence Integrity 3D-IC Platform Faster Multi-Chiplet Design for Automotive & AI As demands for higher density greater bandwidth and lower power accelerate 3D-IC technology is transforming semiconductor design. By enabling vertical stacking of chiplets and advanced packaging 3D-IC delivers smaller form factors better performance and lower costs. Cadences Integrity 3D-IC platform is the industrys first integrated system and SoC-level solution for planning implementation and signoff of 2.5D and 3D stacked designs. Built on the Innovus digital implementation system it supports heterogeneous" [YouTube Link](https://youtube.com/watch?v=1ePkLZGM-Rc) 2025-05-20T18:50Z 40.6K followers, [---] engagements "What Is Clock Skew in VLSI Design Types Causes & Impact on Timing Closure Clock skew is a critical concept in synchronous digital circuits influencing timing closure and overall chip performance. In this video we explain what clock skew is why it occurs and the different types - positive skew negative skew and zero skew - with their impact on setup and hold timing. Clock skew refers to the difference in arrival times of the clock signal at different sequential elements like flip-flops. Ideally the clock should reach all points simultaneously but physical factors such as wire delays and" [YouTube Link](https://youtube.com/watch?v=1gPzIpBsFO0) 2025-11-14T05:48Z 40.7K followers, [---] engagements "Build Model in Cadence Modus Create Optimized Test Models for ATPG Flow What is Build Model in Cadence Modus The Build Model step creates an optimized test model by reading the design netlist and structural library files combining them into a complete design image. This model is essential for all subsequent steps in the ATPG (Automatic Test Pattern Generation) flow. In this video youll learn : What is Build Model in Modus How it reads netlists and libraries Why an optimized test model is critical for ATPG Example: from Verilog to schematic Timestamps : (00:00) Introduction to Build Model" [YouTube Link](https://youtube.com/watch?v=28xVY3_Aznw) 2025-09-17T18:46Z 40.6K followers, [--] engagements "Verifying Cache With Formal This video shows a very powerful concept in formal called data-tagging and how it can be used in cache verification. #LearnWithCadence #EDA #Jasper Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create" [YouTube Link](https://youtube.com/watch?v=2lyn05jtdEE) 2022-09-09T02:36Z 40.7K followers, [----] engagements "What is an Engineering Change Order (ECO) What is an ECO (Engineering Change Order) and why is it critical in chip design In this video we explain ECOs in detail covering premask ECO and postmask ECO and why these changes are necessary during late stages of design implementation. Youll learn: What happens when a logical error is found after base layers are taped out How spare cells enable postmask ECO without disturbing transistor layers Why routing layer changes differ from netlist changes The role of ECOs in simulation and design correction Whether youre a physical design engineer or" [YouTube Link](https://youtube.com/watch?v=30GiYmUPlN4) 2025-09-11T17:32Z 40.6K followers, [---] engagements "Xcelium Distributed Simulation App Accelerates Multi-Die Simulations Up to 3X Cadence Xcelium Logic Simulator is redefining performance for multi-core machines and multi-die systems. In this video Alok Jain Corporate VP of R&D explains how Xcelium leverages parallelism to overcome traditional simulation bottlenecks and deliver up to 5X speed-up for advanced designs. Key highlights include : Build System: Parallel and incremental build capability delivering 210X faster compilation. Run System: Multi-core acceleration for ATPG DFT designs achieving 35X speed-up. New Features : Multi-core for" [YouTube Link](https://youtube.com/watch?v=4IwBjOhvAfI) 2025-07-14T12:52Z 40.6K followers, [---] engagements "NVIDIA Partners with Cadence to Overcome Chip Design Challenges Find out from Narendra Konda Director Hardware Engineering NVIDIA how Cadence helps them overcome challenges faced while designing the worlds largest GPUs and SoC chips. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables" [YouTube Link](https://youtube.com/watch?v=4gg_y-PEB04) 2020-02-26T20:05Z 40.7K followers, [----] engagements "What Is a DEF File in VLSI Design Role in Physical Layout & Data Exchange The DEF file (Design Exchange Format) is a cornerstone of VLSI physical design enabling accurate representation and seamless transfer of design data across EDA tools. In this video we explain what a DEF file is why it matters and how it supports place-and-route flows timing analysis and design portability. A DEF file captures the exact placement of macros standard cells IO pins and other physical components along with their coordinate information. This ensures precise layout representation and smooth integration between" [YouTube Link](https://youtube.com/watch?v=5jOfqeXoZO8) 2025-11-14T05:46Z 40.6K followers, [---] engagements "Whiteboard Wednesday - Introducing the DFI [---] Interface Standard In this weeks Whiteboard Wednesday John MacLaren chairman of the DDR PHY Interface Group describes the new DFI [---] specification and the enhancements it provides to the Controller/PHY Interface of DDR memory channels. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:" [YouTube Link](https://youtube.com/watch?v=5rfxkt-5T4o) 2018-05-16T16:33Z 40.7K followers, 13K engagements "Cadence Tensilica Making AI "Cool" & Efficient AI is cool but is it efficient Running Artificial Intelligence on battery-powered devices (like AR glasses or Hearables) requires massive processing power without draining the battery. That is where Cadence Tensilica IP comes in. The Solution: Tensilica processors are designed specifically for On-Device AI. By optimizing the Digital Signal Processor (DSP) and Neural Processing Unit (NPU) architectures we enable: Lower Power Consumption: Run complex models with a fraction of the energy. Higher Performance: "AI Boost" technology accelerates" [YouTube Link](https://youtube.com/watch?v=5wobnESW86k) 2025-04-07T17:29Z 40.7K followers, [----] engagements "What are Slew and Transition Times Why do even the fastest chips fail It often comes down to the split seconds between signal states. Thus discover how Slew and Transition times dictate the future of high-speed electronics. In the world of Intelligent System Design we often talk about the "speed" of a processor but rarely do we discuss the journey a signal takes to get there. Every bit of data that moves through a chip must change states from low to high or high to low. This transition isn't instantaneous; it is a physical process that takes time. When a signal "slews" it is fighting against" [YouTube Link](https://youtube.com/watch?v=67ABTQBVb4k) 2026-01-16T08:12Z 40.8K followers, [---] engagements "Introduction to the Cadence Palladium Cloud Solution In this excerpt from EE Journals Chalk Talk series with Amelia Dalton Craig Johnson Vice President of Cloud Solutions for Cadence introduces the Cadence Palladium Cloud solution a convenient way to access emulation capacity for your short-term needs. To learn more visit https://www.cadence.com/go/cloud. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn:" [YouTube Link](https://youtube.com/watch?v=6V0TykuW2bE) 2020-11-11T23:26Z 40.7K followers, [---] engagements "Mastering SKILL Forms in Allegro PCB Editor Cadence Tutorial for axlForm() Automation Unlock the power of automation in PCB design with Cadence Allegro In this tutorial we dive deep into the PCB Editor SKILL API and show you how to create interactive fixed-size forms using the axlForm() functions. Learn how to define form fields handle user input with callbacks and integrate your forms with existing SKILL scripts all within the Cadence Allegro PCB Editor. Topics Covered : (00:00) Introduction to SKILL Forms (00:19) Creating the Form Definition File (01:38) Defining Form Size and Layout" [YouTube Link](https://youtube.com/watch?v=6ZeY5b8UG-w) 2025-03-03T16:39Z 40.6K followers, [---] engagements "GLOBALFOUNDRIES ASIC Design Team Validates Hierarchical Test Architecture with Cadence Test Solution GLOBALFOUNDRIES needed to create a hierarchical test methodology for highly-complex custom ASICs. The challenge was to be able to seamlessly migrate the architecture without design or compute overhead. The Cadence test solution enabled the team to develop such a methodology and reduce significantly both the memory and CPU usage" [YouTube Link](https://youtube.com/watch?v=6ba_z9wlzmo) 2016-11-07T19:26Z 40.7K followers, [---] engagements "What's New in Voltus IC Power Integrity Solution - SSV [-----] In this video you will learn about the key Voltus IC Power Integrity Solution features implemented in the SSV [-----] release. #LearnWithCadence #EDA #Voltus Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic" [YouTube Link](https://youtube.com/watch?v=7y2iuJgK7RI) 2023-05-16T20:42Z 40.7K followers, [---] engagements "AI Driven Data Analytics Improving Design Team Productivity Dr Venkat Thanvantri VP of AI R&D at Cadence explains why AI driven data analytics enables design teams to deliver better chips more quickly by efficiently utilizing the vast quantities of valuable EDA data that is being generated. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:" [YouTube Link](https://youtube.com/watch?v=8B4appAgD8k) 2022-09-13T14:15Z 40.7K followers, [---] engagements "What Is Multibit Cell Inference MBCI This video explains the concept of multibit cell inference for design optimization and it's benefits in synthesis. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon more than 30" [YouTube Link](https://youtube.com/watch?v=8M3-5a5zZ7k) 2024-03-19T15:58Z 40.7K followers, [---] engagements "My VisionBoard: Ian Dennison Cadence Design Systems Ian Dennison Solutions Group Director Custom IC Group at Cadence talks about his personal vision board and the exciting innovations he sees taking place in AI as well as Cadence's contributions to these developments. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:" [YouTube Link](https://youtube.com/watch?v=9u40ATmeD_A) 2018-06-12T13:39Z 40.7K followers, [---] engagements "How Alphawave Semi Uses Cadence Tools for High-Speed Connectivity Design Alphawave Semi delivers industry-leading high-speed connectivity solutions for AI data centers 5G wireless infrastructure autonomous vehicles and storage systems. Their cutting-edge technology enables wired connectivity that is faster more reliable and lower power meeting the demands of next-generation applications. The challenge Completing complex designs under tight schedules without compromising quality. But to overcome these hurdles Alphawave Semi relies on Cadence tools including : Clarity 3D Solver and Clarity" [YouTube Link](https://youtube.com/watch?v=BRfIAlaptM4) 2025-08-15T22:24Z 40.6K followers, [---] engagements "Revolutionizing Chip Design & Verification with Cadence AI Innovations Hear from Ziyad Hanna Corporate Vice President at Cadence as he unveils groundbreaking AI advancements in the verification domain. Learn about Verisium Cadence's cutting-edge AI solution transforming verification with smart bug localization efficient coverage closure and formal verification technologies. Discover how Sim.AI accelerates coverage closure by over 5X and how Jasper Proof Master significantly boosts formal verification productivity. This video also showcases the Cadence Jedi platform designed to propel" [YouTube Link](https://youtube.com/watch?v=CEik6l3Fg7Q) 2025-01-09T01:00Z 40.6K followers, [---] engagements "What Are Gate Array Cells ECO Flow Explained with Cadence Tools What are Gate Array Cells and why are they important in ECO Gate array cells are physical-only cells used during Engineering Change Orders (ECO). A base gate array cell acts like a filler cell and can be replaced with a logical gate array cell during ECO without impacting the base layers. In this video youll learn : What are gate array filler cells How they enable post-mask ECO Why size and symmetry matter for easy swapping Example: replacing filler cells with multiple logical cells Timestamps: (00:00) Introduction to gate array" [YouTube Link](https://youtube.com/watch?v=CQhVWGrm9yQ) 2025-09-17T18:59Z 40.6K followers, [---] engagements "Introducing Cadence HiFi 5s Cache-Coherent Multicore DSP for Next-Gen Audio Audio and voice applications are evolving rapidly across automotive infotainment TVs soundbars PCs earbuds and AR/VR devices. These use cases demand AI processing at the edge object-oriented audio codecs and software-defined vehicles making multicore DSP architectures essential. In this video Prakash Paradapati Marketing Director for Audio DSPs at Cadence introduces the cache-coherent HiFi 5s symmetric multiprocessor a groundbreaking solution that simplifies multicore software development by ensuring hardware-level" [YouTube Link](https://youtube.com/watch?v=D9A6x4FxezI) 2025-06-20T15:44Z 40.6K followers, [---] engagements "What Happens to Nets When the VLSI Router Detects Noise #cadence #computereducation VLSI routing tools use real time Signal Integrity (SI) analysis to detect glitches crosstalk and aggressorvictim coupling. This video explains how SI aware routing improves signal integrity by balancing signal integrity timing and routability. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram:" [YouTube Link](https://youtube.com/watch?v=Ds_l3C8tOyM) 2026-02-06T10:15Z 40.8K followers, [---] engagements "Explore How Samsung SARC Achieved 4X Productivity with Cadence Cerebrus AI Studio Discover how the Samsung Austin Research and Development Center (SARC) unlocked 4X productivity using Cadence Cerebrus AI Studio a breakthrough in AI-driven chip design. In this short but powerful video Alex Spencer Principal Engineer at SARC shares how his team accelerated semiconductor design workflows optimized multiple designs in parallel and enhanced efficiency in high-performance computing (HPC) systems. Cadence Cerebrus AI Studio is transforming the future of EDA (Electronic Design Automation) by enabling" [YouTube Link](https://youtube.com/watch?v=EHAFAAbnphY) 2025-05-07T17:00Z 40.6K followers, [----] engagements "CadenceCONNECT Photonics/Quantum Summit: Driving Innovation in Photonic Design Hear from Gal Jongbloet PhD researcher at IDLab (Ghent University imec) as he shares his experience using Cadence Photonics solutions for designing high-speed electro-optical transceivers and reflects on the value of attending the #CadenceCONNECT Photonics/Quantum Summit. Discover how Cadence tools empower photonic design with adaptable models and how the summit fosters collaboration across photonics quantum computing and optical innovation. Key Topics Covered🔍 Why Cadence tools are essential for photonic design" [YouTube Link](https://youtube.com/watch?v=EMLTJdb7Jzw) 2025-11-12T21:49Z 40.7K followers, [--] engagements "Celtro Is Making Medical Implants Battery-Free Using Cadence Tools Learn how Celtro develops battery-free medical implants using Cadence tools to harvest energy from the human body reducing pacemaker size and surgery risks. This technical spotlight provides Biomedical Engineers and Low-Power Chip Designers with a blueprint for disrupting the MedTech industry by replacing chemical batteries with biological energy harvesting. The Evolution of Bio-Electronic Energy Harvesting In the world of Intelligent System Design the most significant constraint for Medical Implants has always been the" [YouTube Link](https://youtube.com/watch?v=EYRT1AWaqOU) 2026-01-06T20:58Z 40.8K followers, [---] engagements "Butterfly Network Puts Ultrasound on a Chip with Cadence Learn how Butterfly Network used Cadence System Design and Analysis technology to create the worlds first 3D ultrasound imaging system that can be carried in your pocket. #Cadence #3dultrasound #technology Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence" [YouTube Link](https://youtube.com/watch?v=FN_9hnL5XOE) 2022-10-12T16:28Z 40.7K followers, [----] engagements "Glitch and Crosstalk Noise in VLSI: Explained in [--] seconds #cadence #pcbdesign #eda This 60-second video describes how glitch and crosstalkthe two primary noise mechanisms in routed designsimpact signal integrity and timing. Glitches can induce functional failures when spikes propagate through nets while crosstalk can create setup or hold timing violations. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram:" [YouTube Link](https://youtube.com/watch?v=GZFIbmUavSs) 2026-02-04T15:30Z 40.8K followers, [----] engagements "Cadence UCIe Chiplet IP Complete Solution for Multi-Chiplet Design & Verification As high-performance computing (HPC) demands increase for density bandwidth and power efficiency chiplet technology is revolutionizing semiconductor design. Cadence leads this transformation with silicon-proven solutions for die-to-die connectivity advanced packaging and heterogeneous integration. This video introduces Cadences 40Gbps Ultralink solution for 2D standard packages and the Universal Chiplet Interconnect Express (UCIe) ecosystem enabling plug-and-play chiplet integration across diverse dies and" [YouTube Link](https://youtube.com/watch?v=GlDoyFCHra8) 2025-05-20T18:50Z 40.6K followers, [---] engagements "100X Faster Chips: Built with Cadence Tools Neurophos is an AI accelerator chip company thats pioneering a new era of optical computing. Its building optical computing chips that are 100X faster and 100X more energy efficient than todays best GPUs. This breakthrough began with an ambitious goalto shrink the optical transistor by 10000X. To push silicon photonics to a whole new level Neurophos is using Cadences Virtuoso Studio EMX Planar 3D Solver Spectre RF Option and Quantus Extraction Solution." [YouTube Link](https://youtube.com/watch?v=GsjbqKqPyJ0) 2026-02-05T01:08Z 40.8K followers, [---] engagements "What is Clock Skew in VLSI Design #microsoft #tech #dataanalytics Clock skew is a critical concept in synchronous digital circuits influencing timing closure and overall chip performance. In this video we explain what clock skew is why it occurs and the different types - positive skew negative skew and zero skew - with their impact on setup and hold timing. Clock skew refers to the difference in arrival times of the clock signal at different sequential elements like flip-flops. Ideally the clock should reach all points simultaneously but physical factors such as wire delays and routing" [YouTube Link](https://youtube.com/watch?v=H566ae3Bjc4) 2026-01-30T05:00Z 40.8K followers, [---] engagements "New Cadence Allegro Platform Accelerates Design of Compact High-Performance Products Hemant Shah from the Allegro PCB unit at Cadence introduces the launch of the new Allegro platform 17.2-2016 at CDNLive EMEA [----] Cadence European user conference. In this video you will hear about the key enhancements in the new portfolio. For more information on the Allegro technology portfolio please visit www.cadence.com/news/allegro172 cadence allegro PCB CDNS flex design rigid-flex design cadence allegro PCB CDNS flex design rigid-flex design" [YouTube Link](https://youtube.com/watch?v=J1VUquMdNPY) 2016-06-07T14:28Z 40.7K followers, [---] engagements "Announcing Celsius Thermal Solver a new approach to system-level thermal analysis In this week's Whiteboard Wednesdays video Be Gu introduces Celsius Thermal Solver a new tool employing finite element analysis (FEA) techniques for thermal analysis of electronic systems. Ben explains how a novel architecture enables Celsius to deliver 10x capacity and performance improvements over existing solutions. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook:" [YouTube Link](https://youtube.com/watch?v=JrQbCZe9e8c) 2019-09-18T03:59Z 40.6K followers, [----] engagements "Cadence Introduces the Janus NoC System IP As Cadence System Solution Group expands its capabilities to become a system design partner the new addition of the Cadence Janus Network on Chip to the IP portfolio aims to ease system integration and improve time to market. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:" [YouTube Link](https://youtube.com/watch?v=K8rC8GNEEE8) 2024-08-05T21:22Z 40.6K followers, [----] engagements "How @SumitomoElectric Uses Cadence AWR to Design Wideband Amplifiers for Base Stations Sumitomo Electric Industries is pushing the boundaries of microwave amplifier design for shared base stations addressing critical challenges like lower cost reduced footprint and high efficiency. In this video learn how Sumitomo engineers developed a wideband amplifier architecture (MBRA) introduced in [----] designed to deliver micro-efficiency and support next-generation wireless networks. This innovation is essential for achieving shared base station deployments enabling operators to optimize" [YouTube Link](https://youtube.com/watch?v=LIztJZ5RwyM) 2025-08-27T19:59Z 40.6K followers, [---] engagements "How @VoxelSensors Uses Cadence Tools to Build Next-Gen AI Perception Systems The future of intelligent machines starts with intelligent perception and VoxelSensors is leading the way. Todays perception systems are power-hungry slow and fail in real-world conditions like dust fog or rain. They also generate massive amounts of data that processors cant handle resulting in wasted resources and poor user experiences for AR glasses smart assistants and robots. VoxelSensors has cracked the code with its unique sensing software platform delivering : 10x improvement in power consumption for all-day" [YouTube Link](https://youtube.com/watch?v=LhT8-6iwC-c) 2025-09-02T22:49Z 40.7K followers, [---] engagements "NeoLogic Breaks the Limits of CMOS Design with Cadence Tools Discover how NeoLogic uses CMOS+ design and Cadence Innovus to deliver power-efficient AI server CPUs for data centers while optimizing PPA and RTL synthesis. Disrupting Modern CPU Architecture NeoLogic is redefining the semiconductor landscape with its proprietary CMOS+ design technology. By focusing on reducing the complexity of microprocessors rather than just transistor scaling NeoLogic delivers superior power-efficient server CPUs for modern data centers. This innovation integrates seamlessly with the standard CMOS fabrication" [YouTube Link](https://youtube.com/watch?v=N3slOFIz2Dg) 2025-12-23T17:16Z 40.8K followers, [---] engagements "Cadence Design Systems: SEMICON West [----] SEMICON West [----] in San Francisco This is a big event with an amazing opportunity to meet those who connect the electronic systems design community to the electronics supply chain. Cadence booth #2135 to learn about their new design techniques including: large-scale analog verification simulation RF and RFIC module co-design integrated electronics/photonic design automation advanced IC packaging and cross-platform solutions and of course designing in the cloud Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsSQ" [YouTube Link](https://youtube.com/watch?v=NNAs2WQhlz0) 2019-07-09T18:46Z 40.7K followers, [---] engagements "Headphone Spatialization on Tensilica Hi-Fi DSP Cadence & Fraunhofer Demo Master headphone spatialization on Tensilica Hi-Fi DSP. Learn how Fraunhofer & Timbrey Labs optimize 3D audio & real-time algorithm development. This technical deep-dive is designed for Audio SoC Architects and Signal Processing Engineers who need to implement immersive low-latency Headphone Spatialization and Microphone Enhancement in consumer electronics. As [----] standards shift toward personalized spatial audio understanding the integration of Fraunhofer IIS logic onto the Hi-Fi DSP is critical for maintaining" [YouTube Link](https://youtube.com/watch?v=OBFThaVlCxk) 2025-02-13T04:27Z 40.6K followers, [---] engagements "Cadences Insight into Design Process Helps the US Technology Leadership Council Achieve its Goals Find out from Dr. Eric Haseltine Chairman of the US Technology Leadership Council how Cadence brings a unique perspective on designing microelectronics and other systems to the government and how it is helping the US technology and leadership councils goal to promote better understanding between defenseintelligence contractors and the government counterparts. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect" [YouTube Link](https://youtube.com/watch?v=OGIFGUZOwEI) 2020-01-28T18:23Z 40.7K followers, [---] engagements "Why Placement Blockages and Halos Matter in VLSI PnR #cadence #pcbdesign #eda Placement blockages are used to reduce local congestion and prevent detour routing that can degrade timing. Halos act as movable blockages around macros for pin accessibility and avoid placing cells too close to macro pins. Together they help achieve cleaner routing with improved timing and less local congestion. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X:" [YouTube Link](https://youtube.com/watch?v=PUegNpflrpw) 2026-02-02T03:09Z 40.8K followers, [---] engagements "FMEDA for Automotive Safety (Optimize Designs with Cadence MIDAS Platform) Failure Mode Effect and Diagnostic Analysis (FMEDA) is essential for achieving ISO [-----] compliance in automotive systems. Cadences MIDAS Safety Platform delivers a holistic FMEDA-driven methodology integrating safety analysis verification and implementation for analog digital and mixed-signal designs. MIDAS supports two FMEDA modes : Architectural FMEDA for early design phases without detailed data based on estimated failure rates. Detailed FMEDA leveraging actual design hierarchy area gates and flops for accurate" [YouTube Link](https://youtube.com/watch?v=Po9anNZYeIk) 2025-05-20T18:47Z 40.6K followers, [--] engagements "Delivering better PPA and chip design productivity using Cadence Cerebrus Intelligent Chip Explorer Rod Metcalfe ML Product Manager explains how Cadence Cerebrus Intelligent Chip Explorer has enabled a revolution in chip design productivity allowing engineering teams to implement increasingly large and complex system on chips required by the latest 5G autonomous driving hyperscale compute industrial IoT driven products. Cerebrus the Future of Intelligent Chip Design. Find more great content from Cadence: Subscribe to our YouTube channel:" [YouTube Link](https://youtube.com/watch?v=PuW4S9T74Lw) 2021-07-22T12:45Z 40.7K followers, [----] engagements "3DGS Makes Electrical Circuits in Glass Using AWR and OnCloud Learn about how 3DGS scalable process for dynamically sculpting photosensitive glass empowers high-performance electronics using Cadence AWR and OnCloud. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic" [YouTube Link](https://youtube.com/watch?v=PwhEaml03rM) 2022-07-27T16:51Z 40.6K followers, [---] engagements "Cadence RF/Microwave Design at IMS [----] Visit Cadence at the International Microwave Symposium (IMS) to learn about the latest solutions for RF-to-mmWave component and system design including innovations in circuit simulation electromagnetic (EM) thermal analysis and implementation flows across RFICs/MMICs packages/modules and PCBs. Cadence experts demonstrate new features in the AWR Design Environment platform and the advantages of integration with Cadences Clarity 3D Solver Celsius Thermal Solver and EMX Planar 3D Solver as well as the benefits of the benefits of the Virtuoso RF Solution." [YouTube Link](https://youtube.com/watch?v=R9DyRqKhBLk) 2023-06-05T16:45Z 40.6K followers, [---] engagements "Why Chiplets Are the Future of SoC Design Chiplet-based SoC architectures are transforming semiconductor design delivering cost efficiency customization configurability and ecosystem scalability. This presentation explores Cadences chiplet reference platform enabling faster time-to-market and modular system design for automotive robotics aerospace and defense applications. Learn how ARM CSA UCIe and Cadence tools simplify integration while ensuring security and functional safety. Key Highlights : Industry shift : From monolithic SoCs to modular chiplets to overcome reticle limits cost and" [YouTube Link](https://youtube.com/watch?v=RmjNf-bAc4c) 2025-03-25T17:43Z 40.6K followers, [---] engagements "Equal1 Builds the Worlds First Silicon-Based Quantum Computer with Cadence Tools Equal1 is pioneering the worlds first silicon-based quantum computer integrating the Quantum Processing Unit (QPU) and control electronics on a single chip. This breakthrough design operates at [--] Kelvin colder than space and dramatically reduces size wiring and power from [---] MW to just [--] kW making quantum computing practical and scalable. Why Quantum Matters : It matters because Quantum computers use qubits instead of bits enabling exponential compute power for challenges like drug discovery battery material" [YouTube Link](https://youtube.com/watch?v=RsrTVUDwkoQ) 2025-04-08T15:50Z 40.7K followers, [---] engagements "Fujitsu Designing the Worlds Leading Innovations with Cadence Intelligent System Design Fugaku the worlds most powerful supercomputer designed with Cadence by Fujitsu. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the" [YouTube Link](https://youtube.com/watch?v=SPlKLnodCiU) 2020-10-14T18:15Z 40.7K followers, [----] engagements "Faster Timing Signoff with Tempus ECO: Fix Violations & Optimize Power Tempus ECO is a powerful feature in Cadence Tempus Timing Signoff Solution designed to accelerate signoff closure while delivering the best PPA (Power Performance Area) in the industry. In this video learn how Tempus ECO helps designers fix timing violations reduce power consumption and achieve convergence on large complex designs. Tempus ECO offers : 50% faster time-to-signoff closure 2x faster STA performance with DSTA and CMMC Highly robust ECO flow for cleaning up remaining timing violations with minimal iterations" [YouTube Link](https://youtube.com/watch?v=T2OQtfixDuE) 2025-11-20T04:16Z 40.6K followers, [---] engagements "What is Electromigration and IR Drop Analysis This video introduces Electromigration (EM) and IR drop. EM refers to the unwanted movement of materials in a semiconductor. IR drop refers to the voltage drop on metal wires during current flow due to the resistance of metal wires. For more information about Quantus-Tier3 course visit: https://www.cadence.com/en_US/home/training/all-courses/86150.html For more related videos visit https://support.cadence.com/TrainingBytes/QRC (Cadence login required). #learnwithcadence #eda #CadenceQuantus #RLCK Connect with Cadence: Website:" [YouTube Link](https://youtube.com/watch?v=THWkLTSxIPI) 2024-04-18T14:32Z 40.7K followers, 11.7K engagements "Cadence ASK AI Assistant (Faster Debug & Smarter Support with GenAI) Meet Cadence ASK AI Assistant your Generative AI-powered troubleshooting companion designed for designers and engineers. ASK AI revolutionizes learning and support by analyzing vast knowledge bases and delivering context-specific insights in seconds. Why ASK AI matters [--]. Instant troubleshooting: Quickly identify root causes and resolve issues faster. [--]. Smart summarization: Condenses complex debugging and learning collateral into actionable answers. [--]. 24/7 access: Available via ASK Portal homepage or interactive chatbot." [YouTube Link](https://youtube.com/watch?v=THltyoERRhg) 2025-09-25T04:03Z 40.6K followers, [---] engagements "What Is DFT in VLSI Design In this 1-minute video you will understand the concept of DFT (Design for Test). Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon more than [--] years of computational software expertise. The" [YouTube Link](https://youtube.com/watch?v=TdpYVTJVr4w) 2024-07-24T18:09Z 40.7K followers, [----] engagements "TSMC & Cadence Announce N2P A16 and A14 Advancements at Tech Symposium At the recent TSMC Technology Symposium groundbreaking innovations were unveiled to accelerate AI transformation faster computing and greater power efficiency. Hear from Lluis Paris Senior Director at TSMC North America as he shares details on design tool certifications for N2P A16 with Super Power Rail and N3C process plus collaboration on A14 technology a major leap from the industry-leading N2 nanosheet transistor technology. This partnership between TSMC and Cadence reflects a shared commitment to technology scaling" [YouTube Link](https://youtube.com/watch?v=TtcUmEh-VUU) 2025-06-19T14:38Z 40.6K followers, [---] engagements "Voltus Insight AI: Cadences Generative AI Solution for IR Drop Fixes Voltus Insight AI is Cadences AI-driven in-design solution for improving chip power integrity. This video explains how this generative AI technology predicts IR drop issues early and enables timing and DRC-aware fixes across placement power grid reinforcement routing and ECO stages. Youll learn about its four key features : Fast IR inferencing engine: Uses proprietary neural networks for instant feedback on design changes IR drop diagnostics: Deep learning identifies aggressors victims and resistance bottlenecks Multimethod" [YouTube Link](https://youtube.com/watch?v=Urv18DoKXZ4) 2025-11-26T09:55Z 40.7K followers, [---] engagements "Cadence HBM3E PHY @14.4Gbps Cadence HBM3E PHY IP sets the benchmark for high-speed memory interfaces. In this demo our engineers showcase the performance and robustness of the PHY operating at 14.4Gbps TX speed while reading/writing to the HBM3 stack at 10.4Gbps DRAM speed. Key highlights : Aggressive PPA targets for 3nm technology node Robust TX eye diagram with 110mV eye height and 70ps width Loopback mode validation with error-free operation Demonstration of 1D timing margins and 2D eye captures for memory reads Future-proof design for higher DRAM speed grades Why it matters : Higher" [YouTube Link](https://youtube.com/watch?v=VjidNTYJCtI) 2025-10-22T14:13Z 40.7K followers, [---] engagements "The Cadence Digital Full-Flow for SoC Design and Implementation Designs are only getting bigger and more complex and your PPA targets are harder to meet every project. You want a complete design and implementation solution that produces the best PPA in the shortest possible time. This can only be achieved with the Cadence digital full-flow. From Genus synthesis to Innovus layout and Tempus and Voltus signoff with common timing and power engines in the only tight integration of layout timing and voltage signoff tools for superior convergence. Cadence computational software for intelligent" [YouTube Link](https://youtube.com/watch?v=WY2Wnb68U3g) 2020-07-10T17:57Z 40.7K followers, [----] engagements "Stop Repeating ECOs: Repair with Master/Clone Aware Timing Optimization #cadence #pcbdesign #eda In this video discover how Master Clone aware timing optimization lets you fix timing once and automatically apply the repair across every replicated core in a hierarchical chip design. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/" [YouTube Link](https://youtube.com/watch?v=X6ZzXmlBxqI) 2026-02-03T10:13Z 40.8K followers, [---] engagements "Sequans Designs its Future 5G IoT Platform Using Virtuoso RF Solution Learn how Sequans develops its next generation 5G Internet of Things (IoT) platform using Virtuoso RF Solution the comprehensive full-suite solution from Cadence. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables" [YouTube Link](https://youtube.com/watch?v=XSdnNrRA4oA) 2021-11-12T18:39Z 40.7K followers, [---] engagements "Enhancing Power Grid Reliability with Early Rail Analysis (ERA) #cadence #pcbdesign #eda This video introduces Early Rail Analysis (ERA) a methodology used to evaluate powergrid integrity early in the physical design flow. ERA helps designers identify and fix powergrid issues before routing is complete reducing latestage design risks. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram:" [YouTube Link](https://youtube.com/watch?v=YCfechFCzEc) 2026-02-02T10:54Z 40.8K followers, [---] engagements "Samsung & Cadence Partner to Deliver 4nm AI Chip with 1.6B Instances & 22% Power Savings Samsung has achieved a major milestone in semiconductor innovation successfully taping out a multi-billion-instance 4nm AI chip powered by Cadences advanced signoff solutions. This breakthrough demonstrates how cutting-edge EDA tools and strategic collaboration can accelerate design closure optimize power and meet aggressive tape-out schedules. In this video discover how Samsung leveraged Cadence Tempus Timing Signoff Certus Closure and distributed STA technology to overcome the challenges of designing" [YouTube Link](https://youtube.com/watch?v=_iTc0gHVh90) 2025-05-02T19:03Z 40.6K followers, [---] engagements "Neurophos Is Reinventing Optical Computing with the Help of Cadence Tools Neurophos is an AI accelerator chip company thats pioneering a new era of optical computing. Its building optical computing chips that are 100X faster and 100X more energy efficient than todays best GPUs. This breakthrough began with an ambitious goalto shrink the optical transistor by 10000X. To push silicon photonics to a whole new level Neurophos is using Cadences Virtuoso Studio EMX Planar 3D Solver Spectre RF Option and Quantus Extraction Solution." [YouTube Link](https://youtube.com/watch?v=aRsv5K3kh9s) 2026-02-04T17:02Z 40.8K followers, [---] engagements "PA Design with Cadence Virtuoso PDK in Microwave Office and Tower Semis SiGe BiCMOS Technologies Learn how you can accelerate your power amplifier (PA) design using a Virtuoso PDK with Tower Semiconductor's SiGE BiCMOS technology within the Microwave Office design environment. Learn more about Microwave Office software. https://www.cadence.com/en_US/home/tools/system-analysis/rf-microwave-design/awr-microwave-office.htmlutm_source=youtube&utm_medium=video&utm_campaign=pdk&utm_term=07-22 Start a free trial today." [YouTube Link](https://youtube.com/watch?v=bos8r-WKybU) 2022-08-03T18:14Z 40.6K followers, [----] engagements "My VisionBoard: Robert Schweiger Cadence Design Systems Robert Schweiger Director Product Marketing Automotive at Cadence talks about his personal vision board and the exciting innovations he sees in the automotive industry as well as Cadence's contributions to these developments. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:" [YouTube Link](https://youtube.com/watch?v=cB7APiO0NMw) 2018-04-19T09:01Z 40.7K followers, [---] engagements "Ambarella's Edge AI Breakthrough: Powered by @Samsung Foundry and @cadencedesignsystems The future of AI is real-time secure and scalable and that future is Edge AI. In this video discover how Ambarella in partnership with Samsung Foundry and Cadence is redefining AI performance with its latest Edge AI SoC the N1655i. This breakthrough solution delivers industry-leading AI performance per watt enabling real-time decisions at the point of data capture. With the ability to process LLMs and VLMs up to [--] billion parameters while decoding [--] streams of 1080p video at just [--] watts the N1655i sets" [YouTube Link](https://youtube.com/watch?v=dDjUC8pVVRQ) 2025-09-05T18:22Z 40.7K followers, [---] engagements "Hailo [--] AI Vision Processor with Cadence Vision P6 DSP CES [----] Demo Discover the Hailo [--] AI Vision Processor. Learn how Cadence Vision P6 DSP enables real-time object detection and image pre-processing for Edge AI at CES [----]. This technical deep-dive is designed for SoC Architects and Embedded AI Engineers who need to implement high-performance Real-time Object Detection in power-constrained environments. As [----] standards for smart cities and autonomous driving demand higher efficiency understanding the role of the Vision P6 DSP in the Hailo [--] ecosystem is critical for optimizing" [YouTube Link](https://youtube.com/watch?v=dX_VXuXh9sI) 2025-02-13T04:26Z 40.6K followers, [---] engagements "embedded world 2024: Using Low-Power DSPs for In-Cabin Sensing With the advancement of cabin comfort tied into active safety the need for accurate passenger detection localization size (child vs. adult vs. pet) and monitoring (fatigue vital signs road focus) are getting tied up with the advanced driving assist functions of a vehicle to operate safely and provide a great user experience inside the cabin. So it is crucial that the various types of sensors work together within the cabin. RGB-IR + short-range radar + time of flight are some of the upcoming sensing modalities that are penetrating" [YouTube Link](https://youtube.com/watch?v=eMe9T3zvGz8) 2024-05-28T18:44Z 40.6K followers, [---] engagements "The Future of Quantum Computing is Here (with Cadence) Hear from Pouya Dianat PhD Chief Revenue Officer at @QCiQuantumComputingInc as he shares how his team collaborates with Cadence to bring thin-film photonic foundry services and PDK solutions to a broader market. Discover how Cadence tools accelerate product development enable market deployment and foster innovation in photonics and quantum computing. The #CadenceCONNECT Photonics/Quantum Summit is more than an eventits a hub for networking knowledge sharing and exploring cutting-edge technologies beyond the status quo. Pouya explains why" [YouTube Link](https://youtube.com/watch?v=g-us1PgtHTA) 2025-11-13T15:03Z 40.6K followers, [---] engagements "Whiteboard Wednesdays - 3X Faster Design Closure with Quantus Integrated Virtual Metal Fill In this week's Whiteboard Wednesdays video Senior Product Engineering Manager Varun Raj Garapati outlines why traditional metal fill insertion usually at the signoff stage is not recommended for FinFET designs to ensure fastest design closure. The Quantus Integrated Virtual Metal Fill (IVMF) solution offers designers the ability to run virtual metal fill much earlier in the design during post-route optimization stage to reduce ECOs for faster design closure. IVMF functionality is available both" [YouTube Link](https://youtube.com/watch?v=gGVDXpfIlng) 2019-03-27T19:16Z 40.7K followers, [----] engagements "What is an ECO What are challenges of doing a manual ECO Engineering Change Orders (ECOs) are a critical part of the digital design flow especially when last-minute bug fixes or design updates are needed. In this video we explain the difference between manual ECO and conformal ECO and how metal-only ECOs using spare cells or gate arrays can accelerate implementation while minimizing cost and risk. Learn how Conformal ECO helps automate complex changes reduce iterations and ensure timing and DRC compliance especially for large ECOs that are difficult to manage manually. Key Topics Covered :" [YouTube Link](https://youtube.com/watch?v=gcV3id2trkU) 2025-11-06T05:34Z 40.6K followers, [---] engagements "Socionext Is Tackling Large-Scale SoC Designs with Cadence Certus Quantus and Tempus Solutions Socionext is an SoC company that has pioneered its business model to help companies achieve differentiation according to their specific needs. They collaborate closely with their partners worldwide and deliver complete SoC solutions from system design to production quality and control. In advanced technology nodes such as 5nm and 3nm billion-gate full-chip designs face prolonged runtimes and substantial memory usage leading to diminished productivity. To combat these large-scale design challenges" [YouTube Link](https://youtube.com/watch?v=gtvmuQZ5occ) 2024-05-21T21:58Z 40.7K followers, [---] engagements "Cadence Showcases First-Pass Silicon Success for 32GT/s UCIe Gen2 IP Step inside Cadences post-silicon validation lab as we showcase the first-pass silicon success of our 32GT/s UCIe Gen2 IP. This demonstration highlights wide-open receiver eyes error-free performance and fully hardware-based bring-up for rapid validation and simplified integration. Key features include : Two UCIe links tested across 7.4mm and 25mm channels (maximum reach per UCIe spec). Automatic LTSSM training flow handled by FI RTL no external firmware or scripts required. Internal impedance calibration without external" [YouTube Link](https://youtube.com/watch?v=hIH9dutHJyE) 2025-08-05T14:01Z 40.6K followers, [---] engagements "A day in the life as an HR intern at Cadence Ever wondered what it's like to work at a top tech company 👩💻✨ Come spend a day with our HR Intern From coordinating All Hands meetings to drafting internal communications see why Cadence is certified as a Great Place to Work. Its not just about chips and software; its about the people Join Us: Ready to start your journey Check out our careers page ------------------------------------------------------------------------------------------------------------------------------------------------------------------ Connect with Cadence : YouTube:" [YouTube Link](https://youtube.com/watch?v=heCERAm4GOY) 2025-09-11T19:20Z 40.7K followers, [----] engagements "My VisionBoard: Steven Lewis Cadence Design Systems Steven Lewis Product Marketing Director at Cadence talks about his personal vision board and the exciting innovations he sees for the future and how Cadences analog division can enable these innovations. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About" [YouTube Link](https://youtube.com/watch?v=hoR4DnoSHPw) 2018-06-12T07:14Z 40.7K followers, [---] engagements "How New DFT Solution Trims Test Time for Digital Logic Hear Paul Cunningham VP of R&D at Cadence explain how the company's new Modus Test Solution reduces test time for digital logic by up to 3X compared to other available solutionswithout impacting chip size or yield. After watching the video learn more about the Modus Test Solution here: http://bit.ly/1Skbda1" [YouTube Link](https://youtube.com/watch?v=i9fvRx4MlGw) 2016-02-02T18:31Z 40.7K followers, [----] engagements "What is Hold Slack in VLSI Design #cadence #pcbdesign #eda Understanding hold slack is essential for timing closure in any VLSI design. In this video youll learn what hold slack truly means why it occurs and how it impacts real chip sign off. I walk through the hold slack formula explain why it is independent of clock frequency and demonstrate a real STA timing report so you can confidently read Required Time Arrival Time and Slack values. Whether youre preparing for STA interviews or working on timing closure in physical design this video gives you clear intuition practical demos and a solid" [YouTube Link](https://youtube.com/watch?v=iAPr_xphCAM) 2026-02-02T06:57Z 40.8K followers, [----] engagements "Cadence Digital Badge: Flaunt Your Expertise With Cadence Digital Badge Watch this video to explore Cadence Digital Badges and how you can flaunt one The exams can be taken from Training Courses (www.cadence.com) https://support.cadence.com/apex/CosLms_DoceboPagedeeplink=/pages/18/all-courses. Log in to support.cadence.com and search for the desired course or Badge Exam. Find More Information: Check out the currently available certification courses and get information. https://www.cadence.com/content/cadence-www/global/en_US/home/training/become-cadence-certified.html Get a Cadence Digital" [YouTube Link](https://youtube.com/watch?v=iXhh94RgBdE) 2022-05-23T14:26Z 40.7K followers, [----] engagements "CadenceLIVE Silicon Valley [----] Thanks to all who joined us at #CadenceLIVE Silicon Valley for [--] days of exciting keynotes [--] tracks of technical sessions a busy Designer Expo and a test drive in a Formula [--] #McLaren simulator. In case you missed it the technical sessions will be available on-demand soon. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn:" [YouTube Link](https://youtube.com/watch?v=j9AIPFQdXgE) 2023-05-03T15:55Z 40.7K followers, [---] engagements "What Is a Level Shifter Master the physical implementation of Level Shifters. Learn about dual-rail power connections placement constraints and how to optimize timing delays across voltage islands. Physical Design Constraints Level Shifters are not just logical elements; they impose specific physical constraints on the P&R flow. Secondary Power Rails: Since a level shifter needs to "see" both voltages routing can be complex. You often encounter "Multi-row" or "Separate" connection types where the cell needs access to a backup power grid. Placement Strategy: You cannot place a level shifter" [YouTube Link](https://youtube.com/watch?v=jNnGcq2nvvM) 2025-02-20T17:45Z 40.6K followers, [---] engagements "EW 2022: Cadence Tensilica Vision and AI DSP IP Showcased in ADAS Application In this video from Embedded World [----] Amol Borkar demonstrates advanced driver assistance system (ADAS) and 360-degree surround view functions on an Automotive AI Perception Processor from Black Sesame Technologies. The Black Sesame Technologies' A1000 SoC features [--] Tensilica Vision P6 DSPs along with Black Sesame Technologies' own Ultra Deep Learning Neural Network hardware accelerator. Leveraging these two IP the SoC is able to very efficiently perform pedestrian detection street sign detection lane detection" [YouTube Link](https://youtube.com/watch?v=k28ujFU_d24) 2022-08-04T17:32Z 40.7K followers, [---] engagements "Quantus I-DSPF Output Demo Series: Episode [--] (P2P Analysis and Parasitic Visualization) Welcome and welcome back the Quantus DSPF Interactive Output (Quantus I-DSPF Output) Demo Series a five-part exploration of the innovative circuit debugging tool. This series highlights the interactive features seamlessly integrated with Virtuoso Studio to revolutionize the design debugging process for faster design closure. Join us for episode four of the Quantus I-DSPF Demo Series where presenter Raksha Jain covers Quantus resistance and analysis as well parasitic visualization using Quantus I-DSPF" [YouTube Link](https://youtube.com/watch?v=lJb_tp29R5E) 2024-05-29T18:49Z 40.7K followers, [---] engagements "Anirudh Devgan and Cristiano Amon - CadenceLIVE Silicon Valley [----] - Fireside Chat Hear from #Qualcomm CEO Cristiano Amon at #CadenceLIVE Silicon Valley discussing how Qualcomms partnership with #Cadence is fundamental to creating the technologies to enable intelligent computing everywhere Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/" [YouTube Link](https://youtube.com/watch?v=m1RYUKbmS9o) 2024-05-01T14:43Z 40.6K followers, [----] engagements "Explore How NepTech Drives Maritime Decarbonization with Cadence Fidelity CFD Maritime transport is vital for global trade but its also a major contributor to greenhouse gas emissions. NepTech is tackling this challenge by designing low-carbon passenger vessels and work boats integrating electric hybrid and electro-hydrogen propulsion for sustainable maritime solutions. To accelerate innovation NepTech leverages Cadence Fidelity CFD Software as its digital testing facility replicating real-world ship behavior in a virtual environment. This approach reduces computation time while maintaining" [YouTube Link](https://youtube.com/watch?v=mXoBtSFB5b8) 2025-03-27T19:29Z 40.6K followers, [---] engagements "What is the Antenna Effect in VLSI Design The antenna effect is a critical challenge in VLSI physical design impacting chip reliability and yield during semiconductor manufacturing. In this video we explain what the antenna effect is why it occurs and how designers mitigate its risks using antenna rules and diodes. During fabrication steps like plasma etching long metal interconnects can accumulate charge acting like antennas. If this charge discharges into the gate oxide of transistors before they are connected to power or ground it can cause oxide breakdown and even chip failure. Learn how" [YouTube Link](https://youtube.com/watch?v=mfmiDgBZd6c) 2025-11-14T05:50Z 40.6K followers, [---] engagements "My Life at Cadence Jaswinder Ahuja Meet Jaswinder Ahuja Corporate Vice President International Headquarters. Watch this Employee Spotlight interview to hear about Jaswinder's remarkable 30-plus year career at Cadence and what brings him to work every morning. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence" [YouTube Link](https://youtube.com/watch?v=mh9-qBp31VA) 2021-11-24T12:25Z 40.7K followers, [----] engagements "Life as an Application Engineer at Cadence Dual Interview with Helga and Serge Explore the Application Engineer life at Cadence. Learn how analog design tools hardware verification and AI optimization are shaping microelectronics. This technical spotlight is designed for Electronic Engineers and System Architects evaluating professional growth in the EDA sector. In the landscape of Intelligent System Design the Application Engineer (AE) role is the bridge between complex software IP and real-world hardware success. This video provides a granular breakdown of the workflows involved in Analog" [YouTube Link](https://youtube.com/watch?v=mseHIe2-GM8) 2025-02-03T15:16Z 40.7K followers, [---] engagements "UCIe Protocol Transforming Chiplet Architecture and Verification Cadence Explore how Universal Chiplet Interconnect Express (UCIe) is revolutionizing chip architecture moving from monolithic designs to scalable systems of chiplets. This technical deep-dive is designed for SoC Architects and Verification Engineers who are navigating the transition from single-die monolithic chips to System of Chiplets. As AI and automotive demands push silicon beyond the Reticle Limit mastering the UCIe Protocol Stack is essential for maintaining performance and scalability in Intelligent System Design. The" [YouTube Link](https://youtube.com/watch?v=nA6eilj52_0) 2025-02-10T22:40Z 40.7K followers, [---] engagements "Master Cadence ASK Portal AI-Powered Learning & Debugging Made Simple Struggling to debug design issues or learn new methodologies efficiently Discover the Cadence Learning and Support Portal your ultimate destination for AI-powered troubleshooting training resources and expert guidance available anytime anywhere. The Cadence ASK Portal combines a comprehensive knowledge base video library and Generative AI (Gen AI) capabilities to help you resolve issues faster adopt new technologies and become an advanced user of Cadence tools. Whether you need installation and licensing help product" [YouTube Link](https://youtube.com/watch?v=nEGqZYtum8o) 2025-07-07T15:48Z 40.6K followers, [---] engagements "3rd Gen AMD EPYC with V-Cache Technology Powers Cadence Computational Software Cadence and AMD collaborate to enable engineers to create the most innovative products of tomorrow. Together we provide the most powerful computational software on the highest performance processors for technical computing. AMD expands its high performance x86 server processor series for technical computing with the AMD EPYC [----] Series processors with AMD 3D V-Cache technology. And Cadences computational software is tuned to fully utilize the ample cache for large data accesses. The 3rd Gen AMD EPYC processors" [YouTube Link](https://youtube.com/watch?v=ojK57cpH5g8) 2022-03-21T13:05Z 40.7K followers, [----] engagements "How Timing Paths Work in Multi-Supply Voltage Designs #cadence #pcbdesign #eda This video explains how timing paths behave in multisupply voltage (MSV) designs focusing on power domains level shifters and crossdomain timing analysis. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/" [YouTube Link](https://youtube.com/watch?v=pB42cO5ZIj0) 2026-02-05T09:01Z 40.8K followers, [----] engagements "LVS Debugging Thumb Rules Let's explore a few thumb rules for PVS/Pegasus LVS Debugging. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon more than [--] years of computational software expertise. The company applies its" [YouTube Link](https://youtube.com/watch?v=pfofyae77X4) 2024-12-17T17:20Z 40.7K followers, [---] engagements "Keep up with the USB Type-C industry with Cadence Design IP Are you prepared for the markets shift to the USB Type-C specification It appears that every USB device will be converted to the new connector to provide users the single cable experience they desire. But enabling a plug-and-play USB Type-C solution is no picnic. With data rates up to 10Gbps and up to 100W of power USB Type-C is the new connector for exciting next-generation products. Add in DisplayPort support via USB Alternate Modes (Alt Modes) and the design challenges become extremely complex. Get to market faster and with higher" [YouTube Link](https://youtube.com/watch?v=qj4FJLrTqpk) 2016-01-19T22:51Z 40.7K followers, [---] engagements "Cadence CEO Dr. Anirudh Devgan appears on the Acquired podcast at @NVIDIA GTC Join Dr. Satoshi Matsuoka Pat Gelsinger and Dr. Anirudh Devgan in this deep-dive discussion from NVIDIA GTC exploring the past present and future of computing from CUDAs early gamble to AI acceleration and quantum computing breakthroughs. Key Highlights : NVIDIAs CUDA Revolution: How repurposing GPUs for general-purpose computing changed the industry. First GPU Supercomputer: Dr. Matsuokas story of building Sububame and outperforming IBMs Blue Gene. Intels Perspective: Pat Gelsinger on CPU dominance accelerated" [YouTube Link](https://youtube.com/watch?v=qlS52EDtbJg) 2025-03-31T20:14Z 40.6K followers, [----] engagements "Introducing Sigrity SPEEDEM in Layout Workbench This video demonstrates the updates and enhancements made in Sigrity SPEEDEM in the Sigrity and Systems Analysis [------] HF3 release. After viewing this video you will learn about: - Introduction of Sigrity SPEEDEM in Layout Workbench - Postprocessing functionalities in SPEEDEM Generator (SPDGEN) - Improved In-Tool Self Help To know more about the Sigrity products visit https://www.cadence.com/en_US/home/tools/system-analysis/signal-and-power-integrity.html #LearnWithCadence #EDA #SPEEDEM Find more great content from Cadence: Subscribe to our" [YouTube Link](https://youtube.com/watch?v=sak7JzvwfPw) 2021-12-01T18:21Z 40.7K followers, [----] engagements "Cadence Tensilica ConnX DSP 5x Faster Radar-Based Multi-Object Tracking Master radar-based multi-object tracking with Cadence Tensilica ConnX DSPs. Learn how the Kaltera Radar Sensor achieves 5x performance gains over CPUs. This technical overview is designed for Automotive Radar Architects and Signal Processing Engineers who need to implement low-latency high-precision tracking for 4D imaging radar systems in next-generation vehicles. The Evolution of Imaging Radar Processing In the complex environment of autonomous driving Radar-Based Multi-Object Tracking is critical for safety and" [YouTube Link](https://youtube.com/watch?v=tyOBEJ11qiI) 2025-02-13T18:15Z 40.6K followers, [---] engagements "Explore How SJSU Spartan Racing Uses Cadence for EV Design Spartan Racing San Jose State Universitys Formula Electric SAE Team is preparing the next generation of engineers by combining classroom learning with real-world design challenges. This video showcases how Cadence Academic Network supports student innovation through industry-leading tools like Cadence Fidelity CFD for thermal and aerodynamic simulations. From brake rotor cooling analysis to heat dissipation studies Cadence solutions help students optimize performance reduce costs and accelerate design cycles. With over [---] active team" [YouTube Link](https://youtube.com/watch?v=uOqVUe-vpCY) 2025-05-19T17:10Z 40.6K followers, [---] engagements "My Life at Cadence: Alessandra Nardi Software Engineering Group Director Automotive Solutions Alessandra Nardi is a software engineering group director in the Automotive Solutions Group at Cadence. She loves engineering because it provides the opportunity to build solutions. Learn about her life at Cadence and her thoughts on how great teamwork leads to success. Help us shape the future: https://www.cadence.com/en_US/home/company/careers.html Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence:" [YouTube Link](https://youtube.com/watch?v=vOHOUr_u6r0) 2020-05-13T18:26Z 40.7K followers, [----] engagements "What Are Aborts in Conformal Equivalence Checker Cadence Best Practices What are aborts and why do they occur during equivalence checking When comparing two designs Conformal Equivalence Checker may encounter situations where a compare point cannot be conclusively determined as equivalent or non-equivalent. These unresolved points are called aborts. In this video youll learn : What aborts are in equivalence checking Why large cones dont cares and complex logic cause aborts How runtime optimization leads to aborts Best practices to avoid aborts during RTL coding and synthesis Timestamps :" [YouTube Link](https://youtube.com/watch?v=vQSvKmKxKLw) 2025-09-17T19:01Z 40.6K followers, [--] engagements "The Hidden Role of Lock Up Latches in Semiconductor Chip Design #cadence #eda #pcbdesign In this 2.5-minute video you will learn what lockup latches are why theyre essential in scan chains and how they prevent clockdomain timing violations. Learn how these transparent latches preserve scan data manage skew and ensure reliable multiclock scan shiftingall automatically handled during scan stitching by synthesis and ATPG tools. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook:" [YouTube Link](https://youtube.com/watch?v=vnrps37wsW8) 2026-01-28T03:42Z 40.8K followers, [----] engagements "Cadence: Your Complete Solution for Disaggregated Design Success Designing high-performance disaggregated architectures for AI and HPC systems is complex. It requires silicon-proven UCIe IP robust verification and rapid signoff workflows all integrated for speed and predictability. Cadence delivers a complete solution : UCIe IP : Peer-reviewed silicon-proven for inter-die connectivity at speeds up to 64Gbps Verification IP : Accelerates coverage using UVM / System Verilog ensuring compliance with UCIe [---] and [---] standards : Integrated design & signoff : Achieve rapid closure without" [YouTube Link](https://youtube.com/watch?v=vxM4lj3TUno) 2025-10-22T22:02Z 40.7K followers, [---] engagements "Cadence PCIe [---] Demo [---] GT/s Electrical & Optical Link Performance PCIe Gen [--] is here and Cadence is leading the way In this demo Cadence engineers showcase a PCIe 7.0-compliant DUT operating at [---] GT/s PAM4 signaling on a 3nm test chip validated using a [--] GHz real-time oscilloscope. Watch as we demonstrate wide-open eye diagrams discuss Gen [--] CDR settings and highlight how performance will improve with full Gen [--] software integration. Plus see our optical link demo featuring linear pluggable optics and DR8 fiber loopback achieving an impressive pre-FEC BER of 2E-8 well below PCIe 7.0" [YouTube Link](https://youtube.com/watch?v=xI5VC6oTQd8) 2025-06-27T01:08Z 40.7K followers, [---] engagements "What are DRC and LVS in Physical Verification This content describes the purpose of running DRC and LVS verification on the design. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon more than [--] years of computational" [YouTube Link](https://youtube.com/watch?v=xclq0wuIruw) 2024-06-07T03:45Z 40.7K followers, [----] engagements "Pointcloud Is Making 3D Imaging Sensors Ubiquitous Through a Single Chip Imagine a world where robots see as clearly as humans. Discover how Pointcloud is using Silicon Photonics to make 3D imaging as common as your phone camera. In the history of technology certain inventions redefine our relationship with the world. The CMOS (SIMOS) image sensor changed everything for Photography and Video making 2D imaging a part of our daily lives. Today we are standing at the threshold of a new revolution. Pointcloud is on a mission to make 3D imaging just as ubiquitous. By creating a single Chipset that" [YouTube Link](https://youtube.com/watch?v=xjYROQGAgb8) 2026-01-20T20:51Z 40.8K followers, [---] engagements "The Power of Cadence Culture Learning Diversity and Team Spirit Discover the Cadence Company Culture in Grenoble. Explore the One Team framework Engineering Career Development and global tech collaboration logic. This technical spotlight is designed for Software Architects and Hardware Engineers evaluating the long-term growth potential of a career at Cadence. In the landscape of Intelligent System Design the speed of innovation is gated by the quality of a team's synchronization. This video provides a granular look at the One Team Culture at Cadence and how it serves as a foundation for" [YouTube Link](https://youtube.com/watch?v=yhaHOtz9Guc) 2025-02-03T15:16Z 40.6K followers, [---] engagements "How to Back Annotate the Schematic in the Allegro X System Capture Project Did you swap pins or rename components in your layout Don't waste time manual-typing Discover the Allegro X back annotation flow to sync your design instantly. In the fast-paced world of hardware engineering the journey from schematic to board is rarely a straight line. Often during the PCB layout phase an engineer realizes that a pin swap or a component rename is necessary to optimize routing. In traditional workflows manually bringing those changes back to the drawing board is a recipe for error. At Cadence we" [YouTube Link](https://youtube.com/watch?v=zR78-IQGNvY) 2025-01-27T18:17Z 40.6K followers, [---] engagements ""Build it Right the First Time" Cadence at Paris Air Show In this talk given at the Paris Air Show James Chew from Cadence talks about the how the Test and Evaluate Before You Fabricate product development methodology once exclusive to semiconductors is now becoming increasingly more relevant to the aerospace industry. James presents the benchmark suite of Cadence tools that allows companies to be the first to market with gotta have aerospace products and systems. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html" [YouTube Link](https://youtube.com/watch?v=-AjWy_fyyh0) 2025-06-26T15:40Z 39.8K followers, [---] engagements "Your Semiconductor Chips Aren't Safe: The Hidden Attack Surfaces Nobody Talks About #cadence #eda In this 1-minute video you will get a quick overview of attack surfaces and vulnerability types in the EDA flow. This training byte breaks down logic digital and analog/mixedsignal attack vectorscovering sequence manipulation sidechannels Trojan insertion fault injection timing/power/thermal exploits and glitch/RFbased attacks. Perfect for understanding how diverse hardware threats emerge across design layers and why securing silicon requires a multidimensional approach. Connect with Cadence :" [YouTube Link](https://youtube.com/watch?v=-IvlRsny-JM) 2026-01-23T11:45Z 40.8K followers, [---] engagements "Cadence Employee Spotlight: Lady Payan Cepeda Introducing Lady Payan Cepeda a Cadence Intern based in our Cambridge office. In this employee spotlight Lady discusses what inspired her to pursue a technical degree how she believes her internship at Cadence will impact her career and offers invaluable advice to students starting their studies. Click the link in our bio to check out the full video 📽 Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q" [YouTube Link](https://youtube.com/watch?v=-Rb1_f1icZU) 2025-02-17T17:22Z 36.5K followers, [--] engagements "Sunday Brunch 11th October Find more great content from Cadence: https://www.cadence.com/ https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes Paul McLellan serves up blogs for the week with the latest cutting-edge technology available at Cadence Design Systems. ************************************************ Monday: Jasper User Group [----] Preview Tuesday: Innovus Mixed Placer Wednesday: TSMC OIP: Rent's Rule and Fast SerDes IP Thursday: Bessemer Ventures: The Memos That Didn't Get Away Friday: Optimized Digital Design Implementation and Signoff on TSMC N3 Featured Post: We Have" [YouTube Link](https://youtube.com/watch?v=0oRah8lCf4M) 2020-10-11T07:00Z 39.9K followers, [---] engagements "Cadence CFD Simulations Are a Key Plank in EV Maritimes Design Validation Process Auckland New Zealands EV Maritime is not just developing high-performance electric boats they are looking to help cities transform their transport systems providing cleaner and more efficient mass transit options to help us all out of our private vehicles and into active and public transport. These days computational fluid dynamics (CFD) simulation is the fastest most accurate and most powerful tool to explore design variations for efficient hull shapes. EV Maritime chose Cadence for their CFD simulations" [YouTube Link](https://youtube.com/watch?v=0shUIj9Hs6w) 2022-12-09T22:23Z 39.9K followers, [----] engagements "What Is Dynamic Pattern Fault Static testing isn't enough 🛑 A "Dynamic Pattern Fault" models defects that only appear under specific timing conditions or sequences. Unlike a simple "Stuck-at" fault this requires defining Initial Values + Propagated Values to catch complex issues like Cross-Talk and Shorted Nets. ------------------------------------------------------------------------------------------------------------------------------------------------------------------ Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn:" [YouTube Link](https://youtube.com/watch?v=0vvPmzBfOu8) 2025-12-18T06:52Z 40.5K followers, [---] engagements Limited data mode. Full metrics available with subscription: lunarcrush.com/pricing
@cadencedesignsystems Cadence Design Systems
Cadence Design Systems posts on YouTube about systems, design, ai, what is the most. They currently have [------] followers and [---] posts still getting attention that total [-----] engagements in the last [--] hours.
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Social Influence
Social category influence stocks technology brands finance events countries automotive brands travel destinations social networks currencies formula 1
Social topic influence systems, design, ai, what is, shorts, ip, tools, flow, in the, cadence
Top accounts mentioned or mentioned by @cadence @cadencecom @nvidia @samsung @intel @thesee @danfoss @sumitomoelectric @voxelsensors @144gbps @qciquantumcomputinginc @baylor @globalfoundries @zfgroup @anirudh @vlsidcon @carnamavlogs
Top assets mentioned GlobalFoundries (GFS)
Top Social Posts
Top posts by engagements in the last [--] hours
"State Space Decoded: How SimAI Optimizes Random Testbenches for Faster Coverage Random testbenches are powerful but without intelligent constraint management they can hide bugs and delay coverage closure. In this episode of Espresso & Electronics we explore how Cadence Xcelium SimAI Exploration Solver transforms verification by analyzing state space identifying coverage holes and guiding randomization toward under-tested regions. Learn why traditional constraint tweaking often leads to over-constrained or under-constrained testbenches and how SimAI helps achieve faster coverage closure"
YouTube Link 2025-11-12T03:45Z 40.7K followers, [---] engagements
"Conquer Coverage Gaps with Verisium SimAI Elevate Your Software Game" Learn how shifting left in your testing process can uncover those elusive bugs that traditional methods might miss. We delve into how machine learning is transforming software simulation and verification targeting coverage holes rare failures and streamlining regression compression to ensure bug-free designs faster and more efficiently. Whether you're a developer or a verification engineer this episode provides practical insights into the evolving strategies for ensuring software reliability. If you missed the webinar on"
YouTube Link 2024-07-09T17:18Z 40.7K followers, [---] engagements
"Using the Cadence VirtualBridge Emulator with the Palladium Platform Narenda Konda Director of Hardware Engineering at Nvidia talks about how the Cadence VirtualBridge Emulator streamlines their emulation flow allowing them to extract more ROI from their investment in emulation technology. Cadence Cadence Design Systems Nvidia Narendra Konda Emulation VirtualBridge Emulator Palladium Palladium Z1 EDA EDA Tools Cadence Cadence Design Systems Nvidia Narendra Konda Emulation VirtualBridge Emulator Palladium Palladium Z1 EDA EDA Tools"
YouTube Link 2017-04-21T18:54Z 40.7K followers, [----] engagements
"STMicroelectronics New flow for analog top level design CDNLive EMEA [----] had several customer experts present innovative tool and design flows to attendees. Watch as Elena Raciti from STMicroelectronics explains how her team used Virtuoso ADE Product Suite in a new flow for analog top level design and went from a manual project management flow to a fully automated design flow. STMicroelectronics Cadence Cadence Design Systems EDA EDA Tools Virtuoso Virtuoso ADE CDNLive CDNLive EMEA CDNLive [----] STMicroelectronics Cadence Cadence Design Systems EDA EDA Tools Virtuoso Virtuoso ADE CDNLive"
YouTube Link 2017-06-13T22:25Z 40.7K followers, [---] engagements
"Arm and Cadence Showcase AI System Collaboration at AI Infra Summit [----] At AI Infra Summit [----] Arm and Cadence spotlight a transformative partnership shaping the future of AI infrastructure. As workloads scale beyond traditional paradigms the industry is shifting from commodity servers to custom-built silicon and this collaboration is leading the charge. Key discussion points : [--]. Arm Neoverse compute subsystems integrated with Cadence IP : HBM4 for AI training LP6 for inference PCIe Gen7 for cluster scaling and UCIe64 for chiplet integration [--]. Early validation with Palladium Z3 emulation"
YouTube Link 2025-10-28T22:36Z 40.7K followers, [---] engagements
"Cadence solutions for the latest PCIe [---] and [---] specifications Preview our solutions for PCIe [---] and [---] at the PCI-SIG Developers Conference encompassing PHY and Controller IP Verification IP and Accelerated VIP/Emulation. Future-proof your designs with our industry leading high performance low power offerings . For more information visit us at https://www.cadence.com/en_US/home/tools/ip/design-ip/discover-pcie5.html Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website:"
YouTube Link 2021-05-24T22:33Z 40.7K followers, [----] engagements
"Keep up with the revolutionCadence Cerebrus Intelligent Chip Explorer Training To meet increased demands of our increasingly connected world semiconductor chips need to be designed faster smaller and smarter. Cadence Cerebrus is a revolutionary and game-changing chip optimization solution enabling this. Join Cadences Cerebrus Intelligent Chip Explorer Training and learn how to use Cadence Cerebrus to scale and automate your design improve your productivity and much more The Online class is free for all Cadence customers with a Learning and Support account. Check out the course details:"
YouTube Link 2023-07-24T13:52Z 40.7K followers, [---] engagements
"Cadence Reality DC for Enterprise Data Centers Explore how enterprise data center teams use Cadence Reality DC to assess and manage deployments virtually before implementation in their data center digital twin. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader"
YouTube Link 2024-03-18T22:00Z 40.7K followers, [---] engagements
"Cadence Ranked #36 on Peoples Companies That Care List Cadence is proud to be recognized as #36 on Peoples Companies That Care list This achievement reflects our commitment to fostering a culture of care innovation and collaboration. At Cadence we empower the worlds most innovative companies to design extraordinary products from chips to boards to complete systems for dynamic markets like hyperscale computing 5G communications automotive mobile aerospace consumer electronics industrial and healthcare. Our Intelligent System Design strategy combines cutting-edge software hardware and IP to"
YouTube Link 2025-09-09T18:14Z 40.7K followers, [---] engagements
"Cadence RTL-to-GDSII Flow Training Your Gateway to Digital Design Traditional design flows can be slow and fragmented. Todays engineers need faster smarter ways to learn and execute. The Cadence RTL-to-GDSII Flow Training Course is your gateway to mastering the complete ASIC design journey from RTL coding to GDSII output in just [--] hours. Why take this course [--]. Learn end-to-end digital design flow [--]. Hands-on experience with seven Cadence tools [--]. Adaptive learning with interactive quizzes [--]. Accelerated training with pre-quiz skip option What youll cover : RTL coding in VHDL or Verilog"
YouTube Link 2025-10-07T19:47Z 40.7K followers, [---] engagements
"From Design to Operations: Thse Data Centers Digital Twin Transformation with HPE and Cadence Thse Data Center a Tier [--] certified colocation provider near Paris has redefined how data centers are designed and operated. This video explores how Cadence Reality DC Digital Twin and HPE enabled a state-of-the-art facility with six halls optimized for mixed and high-density server hosting. Key highlights : Digital twin for design validation: Prevent hotspots optimize cooling and validate high-density rack layouts Physics-based CFD thermal modeling: Predict outcomes under normal and failover"
YouTube Link 2025-10-24T19:59Z 40.7K followers, [---] engagements
"Cadence 224G-LR PHY Transmitter Performance Cadences 224G-LR PHY IP is designed for next-generation 800G and 1.6T networks powering AI factories hyperscale data centers and scale-up/scale-out architectures. This video demonstrates transmitter (TX) performance at 212.5Gbps showcasing wide-open PAM4 eyes error-free operation and compliance with industry standards. Key highlights include : PHY IP versatility: Supports long-reach (LR) and short-reach (SR) channels Data rate range: 1.25Gbps to 225Gbps for Ethernet Ultra Ethernet and CXL Advanced DSP and SerDes integration for signal integrity and"
YouTube Link 2025-07-18T20:56Z 40.7K followers, [----] engagements
"The Hidden Role of Lock-Up Latches in Semiconductor Chip Design Unlock the secret to flawless multi-clock designs. Discover how Lock-Up Latches eliminate timing violations in your scan chains for 100% data integrity. In the high-stakes world of Intelligent System Design the path from a netlist to a working chip is fraught with timing hazards. While functional operation usually takes center stage the Design for Test (DFT) phase introduces its own unique set of challenges. This is where the Lock-Up Latch steps in. As a specialized sequential element it is strategically inserted into the scan"
YouTube Link 2026-02-09T13:00Z 40.8K followers, [---] engagements
"Lip-Bu Tan & Anirudh Devgan on AI Foundry Leadership & Semiconductor Innovation Join @Intel CEO Lip-Bu Tan and @cadencedesignsystems CEO Anirudh Devgan in this exclusive fireside chat at #CadenceLIVE [----] where they share transformative insights on AI strategy semiconductor innovation and engineering culture. Discover how Intel is redefining its approach to agentic AI physical AI and purpose-built silicon while Cadence accelerates design with EDA SDA and advanced tools like Palladium and Millennium. Explore the future of foundry services advanced packaging and system-level design and learn"
YouTube Link 2025-05-14T04:25Z 40.7K followers, [----] engagements
"What Is Shift Left Vulnerability In this 2.3-minute video you will learn how the ShiftLeft approach is transforming security and verification in modern electronic design. By moving security analysis earlier in the design cycle engineers can proactively detect and resolve vulnerabilities long before fabrication. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/"
YouTube Link 2026-02-12T05:17Z 40.8K followers, [--] engagements
"Whiteboard Wednesday - Introduction to ADAS with a Real-Life Example In this weeks Whiteboard Wednesday Marc Greenberg walks us through a typical ADAS system architecture and then provides a real-life testimonial on the value of these systems. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence"
YouTube Link 2018-06-20T16:54Z 40.7K followers, 45.4K engagements
"Cadence ChipStack AI Super Agent Demo -------------------------------------------------------------------------------------------------------------------------------------- Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About Cadence"
YouTube Link 2026-02-10T16:13Z 40.8K followers, [---] engagements
"Cadence CEO Anirudh Devgan Reveals AI Breakthroughs on Mad Money with Jim Cramer AI is reshaping industries and Cadence Design Systems is at the forefront. In this exclusive Mad Money interview CEO Anirudh Devgan shares how Cadence is driving breakthroughs with the Millennium M2000 AI Supercomputer powered by NVIDIA Blackwell technology enabling digital twins for chip design 3D IC automotive aerospace and even drug discovery. Learn how Cadence combines AI-driven design automation with its recurring software business model delivering 80x faster performance and 20x lower power for next-gen"
YouTube Link 2025-05-21T17:25Z 40.7K followers, [----] engagements
"Semiconductor [---] Have you ever wondered about those chips inside your smartphone How are they designed and manufactured Cadences Paul McLellan walks you through how chips get from an idea to a completed design and how the manufacturing process turns sand into valuable electronics. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:"
YouTube Link 2022-08-24T18:12Z 40.7K followers, 19K engagements
"Computational fluid dynamics (CFD) and thermal management Cadence CFD and thermal solutions Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live work and play."
YouTube Link 2022-06-23T15:14Z 40.7K followers, [---] engagements
"Top Five Reasons why you Should Consider a Career as an Application Engineer Discover the top five reasons why you should consider a career as an application engineer at Cadence in this informative video featuring Laya Valsaraj Principal Application Engineer. With over [--] years of experience Laya shares valuable insights into the responsibilities and benefits of this role. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook:"
YouTube Link 2023-05-30T14:25Z 40.7K followers, [----] engagements
"Employee Spotlight: Amit Sharma At Cadence the Application Engineer role is something where you have a vast horizon to explore and you have the opportunity to work on end-to-end flow. - Amit Sharma Sr. Principal Application Engineer Cadence. Watch this short video to know Amits favourite part about working with Cadence and what he enjoys most about his job. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign"
YouTube Link 2023-05-30T14:17Z 40.7K followers, [----] engagements
"Designing an automotive graphics display controller with Stratus HLS In this Expert Insights Video Socionexts Tim Papenfuss discusses how and why they used SystemC and Stratus high-level synthesis (HLS) to design their SC1701 automotive graphics display controller. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:"
YouTube Link 2018-11-14T19:52Z 40.7K followers, [---] engagements
"Anirudh Devgan and Jensen Huang - CadenceLIVE Silicon Valley [----] - Fireside Chat Hear from Jensen Huang at #CadenceLIVE as he discusses the pivotal role of #AI and accelerated computing in shaping industry mega-trends and how #Nvidia and #Cadence are collaborating to drive transformational change across EDA SDA digital biology and AI. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn:"
YouTube Link 2024-04-19T15:07Z 40.7K followers, 37.3K engagements
"Static vs Dynamic EM Extraction in AWR Microwave Office Information about Static vs Dynamic EM Extraction in AWR Microwave Office. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon more than [--] years of computational"
YouTube Link 2024-06-06T17:38Z 40.7K followers, [---] engagements
"Cadence AI: Transforming the World of Electronic Systems with AI From AI-driven IC and SoC design AI-powered verification and AI-guided PCB design to AI-based multiphysics analysis and AI in digital biology Cadence is harnessing the power of AI to usher in a new era of on-device AI IP and next-generation AI chip creation. In this video learn about the incredible connection between cutting-edge AI chip development and the tangible products that exist all around us. From code to cradle and simulation to satellites AI chips are the driving force behind the technology you rely on every day."
YouTube Link 2023-10-02T18:54Z 40.7K followers, [----] engagements
"Chip-2-System Power Signoff Part 3: Voltus and Celsius Integration The Chip-2-System Power Signoff video series shows how Voltus IC Power Integrity Solution integrates with key Cadence products to achieve faster system-level power integrity analysis and closure. The third part in this series presents a high-level overview of Voltus IC Power Integrity Solution integration with Celsius Thermal Solver for analyzing the complex interactions between electrical and thermal responses across chip package board and chassis. #LearnWithCadence #EDA #voltus Find more great content from Cadence: Subscribe"
YouTube Link 2022-12-06T16:24Z 40.7K followers, [----] engagements
"3D-IC design analysis and implementation - Cadence Integrity 3D-IC platform Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live work and play. Cadence"
YouTube Link 2022-06-23T15:25Z 40.7K followers, [----] engagements
"Employee Spotlight: Steven Hollands from the Cadence Cork office Meet Steven Hollands Software Engineering Group Director from our Cork office. In this #EmployeeSpotlight video Steven speaks about what makes him proud to work at Cadence. For six years in a row Cadence has been recognized as a best place to work in Ireland. Come join our team and make your mark Check out our latest job openings - https://bit.ly/cdnsireland #BestWorkplaces #CadenceDesignSystems #GPTW #Hiring Find more great content from Cadence: Subscribe to our YouTube channel:"
YouTube Link 2021-08-11T13:26Z 40.7K followers, [---] engagements
"How to Simulate Chiplets 3x Faster with Xcelium Chiplet-based multidie SoCs promise better yield scalability and timetomarket but they also introduce tough verification challenges : variant explosion testbench maintenance interdie interface coverage and endtoend data integrity. In this Cadence Whiteboard session host Aneka Sunanda welcomes Sunil Kashid (Director Samsung SSIR) to break down where to start with multidie verification how to handle homogeneous vs. heterogeneous splits and how Cadence Xcelium Distributed Simulation App helps teams run multidie simulations up to [--] faster while"
YouTube Link 2025-09-23T17:56Z 40.7K followers, [---] engagements
"Conformal AI Studio AI-Powered ECO & Low Power Signoff Cadence Conformal AI Studio introduces AI and ML to revolutionize SoC verification. Built on decades of trusted Conformal technology this next-gen platform delivers : ✔ AI dashboards & ML-driven proof engines for logical equivalence checking ✔ Automated functional ECO generation for efficient implementable patches ✔ Low-power signoff for complex SoCs with hierarchical flows Core Products : ✔ Conformal AI Equivalence: Distributed Boolean equivalence tracking with AI insights ✔ Conformal AI ECO: Pre/post-mask ECO automation for predictable"
YouTube Link 2025-03-13T14:30Z 40.7K followers, [---] engagements
"Cadence Neo NPU Scalable AI IP with Industry-Leading TOPS per Watt Discover Cadence Neo NPU: a scalable AI acceleration IP ranging from [---] to [--] TOPS with industry-leading TOPS per watt and 2D/3D data engines. This technical spotlight is designed for SoC Architects and AI Hardware Engineers who need to balance extreme performance with a strict power envelope. As Edge AI shifts toward [----] standards selecting an IP that offers high TOPS per watt is essential for thermal management in mobile automotive and IoT devices. The Evolution of AI Acceleration IP At CES [----] Cadence introduced a new"
YouTube Link 2025-02-13T18:15Z 40.7K followers, [---] engagements
"My Life at Cadence: Madhuparna Datta This short video introduces Cadences Madhuparna Datta from the UK Cadence office. She explains why she became an engineer and what makes her to enjoy working at Cadence. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and"
YouTube Link 2021-06-16T18:35Z 40.7K followers, [----] engagements
"Super Bowl Spirit & Community Impact: Cadence City Year & Kidango Unite Cadence volunteers rolled up their sleeves and joined over [---] community volunteers for the City Year Bay Area and Kidango "Every Student Deserves a Coach" Service Day. Together volunteers painted a vibrant mural in East Palo Alto transforming spaces that spark creativity and build community pride for local students. As Super Bowl excitement builds at Levi's Stadium in Santa Clara we're proud to keep the spirit of teamwork and impact alive in our own backyard. This is what community is all aboutshowing up collaborating"
YouTube Link 2026-02-10T19:05Z 40.8K followers, [--] engagements
"Jensen Huang & Anirudh Devgan on AI Factories Digital Twins & Future of Design Automation Join #NVIDIA CEO Jensen Huang and #Cadence CEO Anirudh Devgan in an exclusive fireside chat at CadenceLIVE [----] where they unveil the future of AI-driven design automation digital twins and accelerated computing. This conversation explores how agentic AI systems physical AI and AI factories will transform industries from semiconductor design to robotics and life sciences. Discover how Cadence Palladium and the groundbreaking Millennium M2000 platform powered by NVIDIA Blackwell architecture are"
YouTube Link 2025-05-14T22:09Z 40.7K followers, 10.4K engagements
"Wiwynn Provides Energy-Optimized Data Center IT Solutions from Cloud to Edge with Cadence Optimality In the AI era as the signal-data rate is increasing the signal integrity challenges in server designs are also increasing. Wiwynn is committed to providing hyperscale data centers with innovative cloud IT infrastructure. Their mission is to bring the best total cost of ownership (TCO) energy and energy-itemized IT solutions from the cloud to the edge. Learn more about how Wiwynn is developing a new methodology for PCB designs with Cadences Optimality Intelligent System Explorer and Clarity 3D"
YouTube Link 2024-02-20T19:39Z 40.7K followers, [----] engagements
"How Hardware Accurate Manufacturing Correlated Digital Twin Process Works This video explains how hardware-accurate manufacturing correlated digital twin process works. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About Cadence :"
YouTube Link 2026-02-12T05:15Z 40.8K followers, [--] engagements
"What is the Antenna Effect in VLSI Design #cadence #electricalengineering #computereducation The antenna effect is a critical challenge in VLSI physical design impacting chip reliability and yield during semiconductor manufacturing. In this video we explain what the antenna effect is why it occurs and how designers mitigate its risks using antenna rules and diodes. During fabrication steps like plasma etching long metal interconnects can accumulate charge acting like antennas. If this charge discharges into the gate oxide of transistors before they are connected to power or ground it can"
YouTube Link 2026-02-12T10:00Z 40.8K followers, [---] engagements
"High-speed ECU design and analysis Cadence Allegro PCB Design Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live work and play. Cadence software hardware and"
YouTube Link 2022-06-23T15:17Z 40.7K followers, [---] engagements
"What Is a Digital Twin In this 1.3-minute video you will have a quick introduction to digital twinsvirtual models that mirror realworld objects or systems for realtime simulation accurate behavior modeling and continuous monitoring across chip system and RF domains. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/"
YouTube Link 2026-02-12T05:19Z 40.8K followers, [--] engagements
"Introduction to Cadence Cloud Learn more about the Cadence-Managed Cloud and Customer-Managed Cloud offerings and benefits. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming"
YouTube Link 2023-04-18T21:23Z 40.7K followers, [---] engagements
"Cadence CXL VIP Features Explore the features of Cadence Verification IP (VIP) for Compute Express Link (CXL). Learn how this IP verifies CXL.io CXL.cache and CXL.mem semantics across CXL [---] [---] and 3.x standards. Built on Proven PCIe Ecosystem The Cadence CXL VIP leverages the robust architecture of the Cadence PCIe VIP ensuring seamless integration for designs reusing PCIe Physical layers. It supports all critical device configurations: Type 1: CXL.io + CXL.cache (Accelerators) Type 2: CXL.io + CXL.cache + CXL.mem (GPUs/FPGAs) Type 3: CXL.io + CXL.mem (Memory Expanders) Key Capabilities :"
YouTube Link 2025-12-18T14:32Z 40.7K followers, [--] engagements
"The Basics of Design for Testability DFT Rule Checks #automobile #computereducation This asset describes the Basics of Design for Testability (DFT) Rule Checks. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About Cadence : Cadence is"
YouTube Link 2026-02-09T17:15Z 40.8K followers, [---] engagements
"Cadence Enters a New Era with EDA [---] and Cadence JedAI Platform At Cadence we see a great opportunity for our industry to enter a new era of EDA [---] defined by AI-driven platforms that optimize horizontally across multiple runs of many tools throughout an entire system design program. Learn how EDA [---] is bringing all design and verification data together under a unified data platformRTL layouts constraints waveforms coverage reports log files state graphs AI models and metadata with our new Cadence Joint Enterprise Data and AI (JedAI) Platform. Find more great content from Cadence:"
YouTube Link 2022-09-13T14:15Z 40.7K followers, [----] engagements
"FPGA vs Emulation: What Every ASIC Designer Must Know Before Tapeout. #cadence #eda #pcbdesign In this 1-minute video you will learn the complementary roles of emulation and FPGA prototyping in SoC bring-up. Emulation enables fast deep hardware debugging to ensure RTL correctness while FPGA prototyping delivers the speed needed to validate OS drivers and applications. It also highlights common constraintssuch as FPGA storage limitsand reinforces the rule: dont tapeout until the software is confirmed to work as intended. Connect with Cadence : YouTube:"
YouTube Link 2026-01-28T11:02Z 40.8K followers, [---] engagements
"Comparing PDN Simulation to Measurements for AR/VR Products Kundan Chand power integrity engineer Meta Platforms presents a power delivery network (PDN) measurement methodology and correlation exercise compares the simulation results to measurement and discusses the results in one of Signal Integrity Journals Top [--] webinars of [----]. Connect with Cadence: Website: http://www.cadence.com YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:"
YouTube Link 2023-11-30T04:02Z 40.7K followers, [---] engagements
"A Design with Test Circuit #automobile #computereducation #softwarearchitecture This asset is youtube video of a design with test circuit. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About Cadence : Cadence is a global leader in"
YouTube Link 2026-02-09T04:00Z 40.8K followers, [----] engagements
"EDA Security Deep Dive: Attack Types Tools and Testbench Techniques In this video you will get a quick overview of attack surfaces and vulnerability types in the EDA flow. This training byte breaks down logic digital and analog/mixedsignal attack vectorscovering sequence manipulation sidechannels Trojan insertion fault injection timing/power/thermal exploits and glitch/RFbased attacks. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X:"
YouTube Link 2026-02-12T05:14Z 40.8K followers, [--] engagements
"How to Fix Asynchronous Set and Reset Pins Violation #automobile #computereducation Fixing Asynchronous Set and Reset Pins Violation Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About Cadence : Cadence is a global leader in"
YouTube Link 2026-02-09T10:00Z 40.8K followers, [----] engagements
"Characterizing 22FDX Library at GLOBALFOUNDRIES In this video Ning Jin principal engineer on the Digital Design Methodology Team at GLOBALFOUNDRIES discusses how the company overcame library characterization challenges using Cadence Virtuoso Liberate characterization solution to characterize the library for its 22FDX technology. She also talks about how Cadence Virtuoso Variety helped with statistical characterization of their technology's LVF libraries. Ning discussed library characterization at this year's CDNLive Silicon Valley conference. View her presentation Session CUS202 in the"
YouTube Link 2016-05-26T18:21Z 40.7K followers, [----] engagements
"Prevent Pre-Silicon Hardware Attacks: How Shift-Left Secures Your Chip Design#softwarearchitecture In this 2.3-minute video you will learn how the ShiftLeft approach is transforming security and verification in modern electronic design. By moving security analysis earlier in the design cycle engineers can proactively detect and resolve vulnerabilities long before fabrication. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence"
YouTube Link 2026-01-23T00:00Z 40.8K followers, [----] engagements
"Cadence Debuts Industrys First RealTime eUSB2V2 Demo at CES [----] Powered by 3nm Tech Think USB [---] is slow Think again. Discover how Cadence's brand-new eUSB2V2 IP achieves 10x the speed of legacy standards on a cutting-edge 3nm node. Innovation often means taking something familiar and making it extraordinary. The USB interface standard has been a staple of our digital lives for decades but as we move into the era of Advanced node manufacturing the old ways are no longer enough. Enter eUSB2V2 : a Low voltage USB [---] technology designed to thrive where others struggle. At Cadence we believe"
YouTube Link 2026-02-04T23:07Z 40.8K followers, [----] engagements
"Cadence ChipStack AI Super Agent Demo Overview -------------------------------------------------------------------------------------------------------------------------------------- Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/ -------------------------------------------------------------------------------------------------------------------------------------- About"
YouTube Link 2026-02-10T16:13Z 40.8K followers, [----] engagements
"How Sand Converts to Semiconductor Wafer In this video you will discover how ordinary sand transforms into the foundation of modern electronics This video breaks down the semiconductor manufacturing journeyfrom raw silicon extraction and ingot formation to wafer slicing processing polishing and advanced steps like doping lithography etching and EUV patterning. A quick highlevel walkthrough of the [--] essential steps that turn sand into a finished semiconductor wafer. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn:"
YouTube Link 2026-02-12T05:18Z 40.8K followers, [--] engagements
"Employee Spotlight: Ashwini Kulkarni I was always interested in logical reasoning and problem-solving so I chose electronic engineering as I was fascinated by the whole idea of how small circuits made peoples life easy. - Ashwini Kulkarni Principal Application Engineer Cadence. Watch this short video to know Ashwinis favourite part about working with Cadence and what she enjoys most about her job. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook:"
YouTube Link 2023-05-30T14:17Z 40.7K followers, [----] engagements
"Introduction to Cadence-Managed Cloud Service Learn more about the key benefits and features of Managed Cloud Service provided by Cadence for EDA workloads. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end"
YouTube Link 2023-04-18T21:23Z 40.7K followers, [---] engagements
"Quantum Machines Advances Quantum Computing with Cadence AWR Design Platform Quantum computing is unlocking possibilities beyond classical systems from drug discovery and materials research to optimization and cryptography. But building quantum hardware requires precision speed and advanced design tools. In this video Quantum Machines shares how its hybrid control approach powered by the OPX1000 platform eliminates friction between quantum and classical operations enabling real-time feedback error correction and scalable multi-qubit calibration. To achieve this Quantum Machines relies on"
YouTube Link 2025-05-21T23:10Z 40.6K followers, [---] engagements
"Power Integrity in Chip Design: The Sanity Check You Cant Skip #cadence #eda #pcbdesign The design sanity checks are crucial for power integrity validation and early detection of connectivity issues power vias and timing libraries that can prevent design disasters and ensure robust reliable SoCs. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/"
YouTube Link 2026-01-29T16:15Z 40.8K followers, [---] engagements
"Cadence 224G-LR PHY: Receiver Performance Demo for 800G & 1.6T Networks Cadences 224G-LR PHY IP is engineered for next-generation 800G and 1.6T networks enabling AI factories hyperscale data centers and scale-up/scale-out architectures. This video demonstrates receiver (RX) performance showcasing wide-open eyes low BER and advanced diagnostics for high-speed connectivity. Key highlights include : PHY versatility: Supports long-reach (LR) and short-reach (SR) channels Data rate range: 1.25Gbps to 225Gbps for Ethernet Ultra Ethernet and UALink Advanced DSP and SerDes integration for signal"
YouTube Link 2025-07-09T21:04Z 40.6K followers, [---] engagements
"How Cadence & @NVIDIA Are Powering the Fourth Industrial Revolution with Palladium Z3 & Protium X3 The Fourth Industrial Revolution is accelerating because we finally have the computational power to push AI from theory into production. For decades artificial intelligence algorithms existed on paper waiting for the hardware to catch up. With modern GPUs placed squarely in computational mode AI is now practical at scale. Consider NVIDIAs Blackwell GPU : a single device with [---] billion transistors. Designing and verifying something this complex both as an isolated processor and inside a broader"
YouTube Link 2025-03-11T21:20Z 40.6K followers, [----] engagements
"Whiteboard Wednesdays - Introduction to Convolutional Neural Networks (CNN) In this week's Whiteboard Wednesdays video the first in a two-part series Megha Daga explores Convolutional Neural Networks which are biologically inspired models of neurons in the brain. She details how CNN is leveraged in many of today's use cases such as mobile surveillance and automotive"
YouTube Link 2017-03-22T16:24Z 40.6K followers, 76.7K engagements
"Cadence Cerebrus AI Studio: Industrys First Agentic AI Multi-Block Multi-User SoC Design Platform Join Lokesh Korlipara VP of R&D at Cadence as he introduces Cadence Cerebrus AI Studio the industrys first agentic AI-powered multi-block multi-user SoC design platform. Built on advanced AI-driven digital implementation tools this solution accelerates time-to-market by 5X10X enabling engineers to meet aggressive PPA targets while reducing turnaround time. Cerebrus AI Studio combines principled optimization advanced data analytics and AI agents to automate hierarchical design flows. Key features"
YouTube Link 2025-05-07T17:00Z 40.6K followers, [---] engagements
"Or Maltabashi Bar Ilan University Master Thesis Award Recipient Or Maltabashi Bar Ilan University is the recipient of the Cadence Academic Network Master Thesis Award for EDA [----] for his thesis titled "Automatic Guided Physical Implementation of Common Digital Structures." Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:"
YouTube Link 2020-07-23T00:55Z 40.6K followers, [---] engagements
"View Cadence Automotive Offerings with the Automotive Innovation Platform Cadence offers numerous products and solutions targeted for automotive applications. The interactive Cadence Automotive Innovation Platform provides short videos that explain the latest automotive innovations in IP system verification functional safety system analysis chiplets/3DIC CFD and thermal. Learn more about each topic by downloading additional resources like white papers or visit our website at https://www.cadence.com/en_US/home/solutions/automotive-solution.html. Connect with Cadence: Website:"
YouTube Link 2023-11-28T15:47Z 40.6K followers, 530.1K engagements
"Life at Cadence Milan Simon Kmeti on Engineering AI & Recharge Days Meet Simona Cometti Lead Application Engineer at Cadence as she shares why working at Cadence is exciting and rewarding. From a young dynamic environment full of new ideas to opportunities for innovation Simona explains why she never gets bored at work. She also talks about how she uses Cadence Recharge Days to spend quality time with family and friends outside Milan and shares her perspective on Artificial Intelligence (AI) its huge potential and the importance of integrating it into Cadence tools and solutions. Key Topics"
YouTube Link 2025-04-15T03:48Z 40.6K followers, [---] engagements
"How @Thesee Data Center Uses Cadence Digital Twin for Tier [--] Operations Discover how Thesee Data Center a Tier [--] certified colocation provider near Paris is transforming data center design and operations with Cadence Reality Digital Twin Platform. This video highlights the ecological operational and security benefits of integrating digital twin technology into mission-critical infrastructure. Key advantages include : Energy efficiency optimization and improved PUE (Power Usage Effectiveness) Remote capacity planning and real-time monitoring from anywhere Seamless integration with Building"
YouTube Link 2025-09-02T18:24Z 40.6K followers, [---] engagements
"Whiteboard Wednesdays Advantages of the MIPI I3C Interface In this week's Whiteboard Wednesdays video Alex Passi explains the advantages provided by the new MIPI I3C interface. With I3C mobile device sensors can transmit data faster with lower power and simpler routing than with existing interfaces"
YouTube Link 2016-06-01T17:55Z 40.6K followers, [----] engagements
"Cadences Artisan Foundation IP Learn how Cadence Artisan Foundation IP optimizes advanced SOC design through silicon-proven standard cells and SRAM memory compilers to ensure superior PPA targets. The Foundation of Advanced Silicon Design In the competitive landscape of semiconductor manufacturing the Artisan Foundation IP stands as the critical infrastructure for every breakthrough. This suite provides the fundamental building blocks required for complex SOC Design ensuring that your architecture is not only functional but optimized for the most demanding power and performance constraints."
YouTube Link 2025-12-18T21:14Z 40.6K followers, [---] engagements
"AI in RTL-to-GDSII Flow Cadence Webinar on Synthesis & Signoff Ready to accelerate your digital design flow Join Cadence for an exclusive training webinar on the RTL-to-GDSII back-end flow where well explore how AI-driven features simplify synthesis to signoff and boost productivity for physical design engineers. In this 1-hour session Saias Lead Education Application Engineer at Cadence walks you through the latest innovations in tools like Genus Innovus and Tempus covering everything from logic synthesis to timing closure. Whether youre a beginner or refreshing fundamentals this webinar is"
YouTube Link 2025-09-23T16:38Z 40.6K followers, [---] engagements
"Bar-Ilan University Hackathon hosted at Cadence Petah Tikva Cadence Petah Tikva hosted the annual hackaton of the Faculty of Engineering at Bar-Ilan University on June 8-9 [----]. The Hackathon focused on developing defensive solutions for smart cities applied on existing robotics and drones. [---] students accompanied by [--] mentors faculty and industry partners worked for [--] consecutive hours to address technical and operational challenges and develop advanced solutions with practical feasibility. Find more great content from Cadence: Subscribe to our YouTube channel:"
YouTube Link 2023-07-18T22:29Z 40.6K followers, [---] engagements
"Explore How Samsung Achieved 11% PPA Gain with Cadence Cerebrus AI Studio Discover how @Samsung Semiconductor India Research (SSIR) is transforming SoC design workflows using Cadence Cerebrus AI Studio. By leveraging this AI-driven multi-user multi-block chip design platform SSIR achieved 811% PPA improvement on SoC subsystems a significant productivity win. Cerebrus AI Studio empowers engineers with customizable dashboards advanced data analytics and Smart Model Replay to accelerate design closure and optimize performance. From congestion analysis to clock tree debugging this collaboration"
YouTube Link 2025-05-07T17:00Z 40.6K followers, [---] engagements
"Joules Power Calculator Training Empower your Power Searching for solutions to power related challenges What if power consumption was accurate and connected and consistent Wouldnt that be ideal The new Cadence Joules RTL Power Solution closes the gapsrevolutionizing traditional power analysis methods and the power efficiency of RTL. Learn all about the unrivaled features of the new Cadence Joules RTL Power Solution by joining the Joules Power Calculator training expedition. Because the better you understand power the better you can optimize it. Check out the course details."
YouTube Link 2021-08-10T16:12Z 40.6K followers, [---] engagements
"Cadence PCIe VIP Features Verify your next-gen high-speed designs with Cadence PCIe Verification IP (VIP). This video details the complete feature set for PCIe Gen [--] through Gen [---] covering speeds from [---] GT/s to [---] GT/s. Comprehensive Protocol Support : The Cadence PCIe VIP is the industry benchmark for verifying Root Complex Endpoint and Switch designs. It includes full support for: PCIe [---] (128 GT/s): Advanced FLIT formats PAM4 signaling and Forward Error Correction (FEC). NVMe 2.0: Integrated verification for Non-Volatile Memory Express storage protocols. CXL 3.0: Seamless"
YouTube Link 2025-12-18T14:35Z 40.6K followers, [---] engagements
"A Day in the Life of a Lead Application Engineer at Cadence Employee Spotlight Meet Paolo Vernelli Lead Application Engineer at Cadence Milan as he shares what makes Cadence a great place to work. Paolo highlights two key aspects of his experience: Collaboration with Colleagues A supportive team environment that fosters innovation and teamwork. Customer Interaction Direct engagement with customers that creates a dynamic and exciting work culture. Discover how Cadence empowers its employees to thrive in a collaborative setting while working on cutting-edge technologies for global customers."
YouTube Link 2025-04-15T03:48Z 40.6K followers, [--] engagements
"AI-Driven DSPs for Safer Smarter and Immersive Automotive Experiences Cadence Technologies AIdriven DSP for automotive ADAS and smart cabin sensor fusion incabin sensing and lowlatency audio. This talk shows how Cadence Tensilica DSP cores and Neo (NPU/AI accelerator) power modern vehicles: from external sensing (vision radar lidar thermal) to incabin sensing (driver monitoring child presence detection occupant monitoring) and infotainment (immersive sound ANC beamforming). Youll see how DSPs enable state estimation planning & prediction and control with the latency and power efficiency ADAS"
YouTube Link 2025-03-25T17:44Z 40.6K followers, [---] engagements
"Cadence PCIe VIP Complete Feature Overview for PCIe Gen [--] Explore the Cadence PCIe Verification IP (VIP) and its advanced capabilities for verifying PCIe-based designs. This video provides a comprehensive overview of PCIe VIP features supporting PCIe generations [--] through [--] along with related protocols like CXL (1.1 [---] 3.1) CCIX (1.0 [---] 2.0) and NVMe. Cadence PCIe VIP offers : Host device and switch verification across all native and downgraded widths Support for serial and pipe interfaces including NRZ and PAM4 signaling Over [---] timing parameters [----] checkers and [----] configurable"
YouTube Link 2025-04-11T11:59Z 40.6K followers, [---] engagements
"AI-Powered PCB Design (How @danfoss Uses Cadence Allegro X AI) @danfoss a global leader in energy-efficient technologies is leveraging Cadence Allegro X AI to transform its PCB design flow as part of its LEAP [----] strategy. With a focus on Amplify AI Danfoss aims to speed up placement reduce noise and optimize power integrity for advanced boards powering industrial and sustainable solutions. In this video hear how AI-driven PCB design is helping engineers : [--]. Accelerate initial placement for thousands of components [--]. Improve decoupling capacitor positioning for better signal integrity 3."
YouTube Link 2025-09-24T19:02Z 40.6K followers, [---] engagements
"The Surprising Industries Behind the Semiconductor Chip Innovations. #cadence #eda #pcbdesign In this 1-minute video you will explore the major endmarket shaping todays semiconductor industry from the massive smartphone ecosystem to advanced automotive systems aerospace innovation hyperscale data centers life sciences and the rapidly expanding IoT world. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram:"
YouTube Link 2026-01-29T11:10Z 40.8K followers, [---] engagements
"IR Drop in VLSI (How It Impacts Timing Clock Skew & Design Performance) IR drop is one of the most critical challenges in chip design and its impact on timing can lead to serious performance issues. In this video we explain how IR drop affects signal nets clock nets and overall design integrity. Youll learn : Why IR drop causes setup time violations and hold time violations How clock skew introduced by IR drop leads to silicon failures The effect of power rail IR drop on weakened drivers increased delays and reduced noise margins Why nominal voltage swing differs from IR drop voltage swing"
YouTube Link 2025-11-26T09:52Z 40.6K followers, [---] engagements
"Cadence Multi-Protocol PHY Demo: Simultaneous PCIe [---] and 25G Ethernet over a Unified Interface In modern SoCs flexibility isnt optional its essential. This demo showcases Cadence Whistler PHY IP a 32Gbps multi-protocol SerDes solution designed to simplify architectures and accelerate bring-up. Key highlights : Supports PCIe [---] and 25G Ethernet (25G-KR) concurrently over a single PHY Operates from 1.25Gbps to 32Gbps with low latency and long-reach equalization Delivers exceptional power efficiency for high-performance systems Silicon-proven across 7nm to 3nm nodes Why choose Whistler PHY"
YouTube Link 2025-10-08T19:53Z 40.6K followers, [---] engagements
"AI Buildathon Sparks Change at Cadence HQMore Events Coming 🌍 #cadence #eda #ai Our SSG IP EDA and IT teams came together to drive new ideas exemplifying our "One Cadence One Team" spirit and showing the true power of collaboration. Alex Sgouros VP Engineering for Silicon Customer Enablement reflected on the impressive solutions and teamwork displayed throughout the event. He also shared our exciting vision to bring these AI Buildathons to more regionsincluding India China the East Coast Texas and EMEAin the months ahead. Thank you to everyone who participated and made this event"
YouTube Link 2026-01-29T22:15Z 40.8K followers, [---] engagements
"Most Common LVS Errors in Layout and Schematic Here is a quick reference on common issues in schematic and layout related to device extraction during the LVS process. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon"
YouTube Link 2024-12-17T17:17Z 40.6K followers, [---] engagements
"FPGA Prototyping Challenges & Trends Cadence Proteum X3 Explained Welcome to Espresso and Electronics your quick sip of EDA wisdom In this episode host Anukica Sunda talks with Lance Tamura Product Management Director at Cadence about the evolving world of FPGA-based prototypinga critical methodology for validating complex SoCs before tape-out. Lance shares why many companies struggle to build their own prototypes the challenges of FPGA prototyping and why enterprise prototyping platforms like Cadence Proteum X3 are transforming the design process. Learn about partitioning complexity timing"
YouTube Link 2025-11-12T20:00Z 40.6K followers, [---] engagements
"Beginners Guide to How Timing Budgets Improve Hierarchical STA Closure Master hierarchical STA with precise timing budgets. Learn how SDC constraints like set_input_delay and set_load ensure top-level timing convergence. In a modern Intelligent System Design environment monolithic timing analysis is no longer scalable. This video is a designed for STA Engineers and Physical Design Leads who need to decouple block-level implementation from top-level constraints. Without a clear Timing Budget Allocation top-level integration is often plagued by Top-Level Integration Surprises and endless"
YouTube Link 2026-01-28T03:56Z 40.8K followers, [---] engagements
"How MemryX Powers Edge AI with Cadence Design Tools AI is moving from data centers to edge devices and MemryX is leading the way. This video explores how MemryX tackles the challenges of deploying AI at the edge: achieving cloud-level accuracy overcoming power constraints and delivering high performance without advanced cooling. Learn how MemryXs architecture supports 1000+ models without compression pruning or quantization ensuring what you train is what you infer. Key Highlights : AI at the edge (0:08): Why moving from cloud to edge matters for future applications. Challenges (1:09):"
YouTube Link 2025-03-25T16:21Z 40.6K followers, [---] engagements
"Targeting Critical Nets with NDRs for Robust Timing Closure during VLSI PnR #cadence #pcbdesign #eda Timing closed everywhere except a few stubborn paths Non Default Rules (NDRs) are used for critical nets to reduce delay and improve signal integrity. Use NDRs strategically because they consume additional area and may cause routing congestion. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram:"
YouTube Link 2026-02-06T06:30Z 40.8K followers, [----] engagements
"Cadence Community Forums This video is a walk-through on how to access Forums whats in it for a customer and how can the customers take advantage of the Community Recognition Program. #LearnwithCadence #TechnicalForums #CadenceCommunity Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence"
YouTube Link 2023-08-02T14:10Z 40.7K followers, [---] engagements
"What Is Optimization in Digital Implementation (Timing Power & Area Explained) Optimization in digital implementation is the process of iterating through a design to meet multiple objectives : [--]. Timing [--]. Signal integrity (SI) [--]. Power and [--]. Area This video explains what optimization means in the context of physical design flows and why its critical for achieving design closure. Optimization can be broken down into four key areas : [--]. Timing optimization: Ensures paths meet setup and hold requirements [--]. Signal integrity optimization: Reduces noise and crosstalk for reliable operation 3."
YouTube Link 2025-08-04T18:35Z 40.6K followers, [---] engagements
"Raspberry Pi Uses Cadence to Design Computers for Everybody Learn how Raspberry Pi have used Cadence Allegro X Xcelium verification and digital full flow tools to design from PCB to silicon their enormously popular industrial and educational single-board computers. #raspberrypi #cadencedesignsystems Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/"
YouTube Link 2021-12-16T05:56Z 40.6K followers, [----] engagements
"Reviewing and Validating the Alternative EVS Codec Hear from Stefan Doehla Group Manager and Standards Engineer at Fraunhofer IIS as he discusses the alternative EVS codec. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the"
YouTube Link 2021-05-07T07:00Z 40.6K followers, [---] engagements
"Cadence Integrity 3D-IC Platform Faster Multi-Chiplet Design for Automotive & AI As demands for higher density greater bandwidth and lower power accelerate 3D-IC technology is transforming semiconductor design. By enabling vertical stacking of chiplets and advanced packaging 3D-IC delivers smaller form factors better performance and lower costs. Cadences Integrity 3D-IC platform is the industrys first integrated system and SoC-level solution for planning implementation and signoff of 2.5D and 3D stacked designs. Built on the Innovus digital implementation system it supports heterogeneous"
YouTube Link 2025-05-20T18:50Z 40.6K followers, [---] engagements
"What Is Clock Skew in VLSI Design Types Causes & Impact on Timing Closure Clock skew is a critical concept in synchronous digital circuits influencing timing closure and overall chip performance. In this video we explain what clock skew is why it occurs and the different types - positive skew negative skew and zero skew - with their impact on setup and hold timing. Clock skew refers to the difference in arrival times of the clock signal at different sequential elements like flip-flops. Ideally the clock should reach all points simultaneously but physical factors such as wire delays and"
YouTube Link 2025-11-14T05:48Z 40.7K followers, [---] engagements
"Build Model in Cadence Modus Create Optimized Test Models for ATPG Flow What is Build Model in Cadence Modus The Build Model step creates an optimized test model by reading the design netlist and structural library files combining them into a complete design image. This model is essential for all subsequent steps in the ATPG (Automatic Test Pattern Generation) flow. In this video youll learn : What is Build Model in Modus How it reads netlists and libraries Why an optimized test model is critical for ATPG Example: from Verilog to schematic Timestamps : (00:00) Introduction to Build Model"
YouTube Link 2025-09-17T18:46Z 40.6K followers, [--] engagements
"Verifying Cache With Formal This video shows a very powerful concept in formal called data-tagging and how it can be used in cache verification. #LearnWithCadence #EDA #Jasper Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create"
YouTube Link 2022-09-09T02:36Z 40.7K followers, [----] engagements
"What is an Engineering Change Order (ECO) What is an ECO (Engineering Change Order) and why is it critical in chip design In this video we explain ECOs in detail covering premask ECO and postmask ECO and why these changes are necessary during late stages of design implementation. Youll learn: What happens when a logical error is found after base layers are taped out How spare cells enable postmask ECO without disturbing transistor layers Why routing layer changes differ from netlist changes The role of ECOs in simulation and design correction Whether youre a physical design engineer or"
YouTube Link 2025-09-11T17:32Z 40.6K followers, [---] engagements
"Xcelium Distributed Simulation App Accelerates Multi-Die Simulations Up to 3X Cadence Xcelium Logic Simulator is redefining performance for multi-core machines and multi-die systems. In this video Alok Jain Corporate VP of R&D explains how Xcelium leverages parallelism to overcome traditional simulation bottlenecks and deliver up to 5X speed-up for advanced designs. Key highlights include : Build System: Parallel and incremental build capability delivering 210X faster compilation. Run System: Multi-core acceleration for ATPG DFT designs achieving 35X speed-up. New Features : Multi-core for"
YouTube Link 2025-07-14T12:52Z 40.6K followers, [---] engagements
"NVIDIA Partners with Cadence to Overcome Chip Design Challenges Find out from Narendra Konda Director Hardware Engineering NVIDIA how Cadence helps them overcome challenges faced while designing the worlds largest GPUs and SoC chips. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables"
YouTube Link 2020-02-26T20:05Z 40.7K followers, [----] engagements
"What Is a DEF File in VLSI Design Role in Physical Layout & Data Exchange The DEF file (Design Exchange Format) is a cornerstone of VLSI physical design enabling accurate representation and seamless transfer of design data across EDA tools. In this video we explain what a DEF file is why it matters and how it supports place-and-route flows timing analysis and design portability. A DEF file captures the exact placement of macros standard cells IO pins and other physical components along with their coordinate information. This ensures precise layout representation and smooth integration between"
YouTube Link 2025-11-14T05:46Z 40.6K followers, [---] engagements
"Whiteboard Wednesday - Introducing the DFI [---] Interface Standard In this weeks Whiteboard Wednesday John MacLaren chairman of the DDR PHY Interface Group describes the new DFI [---] specification and the enhancements it provides to the Controller/PHY Interface of DDR memory channels. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:"
YouTube Link 2018-05-16T16:33Z 40.7K followers, 13K engagements
"Cadence Tensilica Making AI "Cool" & Efficient AI is cool but is it efficient Running Artificial Intelligence on battery-powered devices (like AR glasses or Hearables) requires massive processing power without draining the battery. That is where Cadence Tensilica IP comes in. The Solution: Tensilica processors are designed specifically for On-Device AI. By optimizing the Digital Signal Processor (DSP) and Neural Processing Unit (NPU) architectures we enable: Lower Power Consumption: Run complex models with a fraction of the energy. Higher Performance: "AI Boost" technology accelerates"
YouTube Link 2025-04-07T17:29Z 40.7K followers, [----] engagements
"What are Slew and Transition Times Why do even the fastest chips fail It often comes down to the split seconds between signal states. Thus discover how Slew and Transition times dictate the future of high-speed electronics. In the world of Intelligent System Design we often talk about the "speed" of a processor but rarely do we discuss the journey a signal takes to get there. Every bit of data that moves through a chip must change states from low to high or high to low. This transition isn't instantaneous; it is a physical process that takes time. When a signal "slews" it is fighting against"
YouTube Link 2026-01-16T08:12Z 40.8K followers, [---] engagements
"Introduction to the Cadence Palladium Cloud Solution In this excerpt from EE Journals Chalk Talk series with Amelia Dalton Craig Johnson Vice President of Cloud Solutions for Cadence introduces the Cadence Palladium Cloud solution a convenient way to access emulation capacity for your short-term needs. To learn more visit https://www.cadence.com/go/cloud. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn:"
YouTube Link 2020-11-11T23:26Z 40.7K followers, [---] engagements
"Mastering SKILL Forms in Allegro PCB Editor Cadence Tutorial for axlForm() Automation Unlock the power of automation in PCB design with Cadence Allegro In this tutorial we dive deep into the PCB Editor SKILL API and show you how to create interactive fixed-size forms using the axlForm() functions. Learn how to define form fields handle user input with callbacks and integrate your forms with existing SKILL scripts all within the Cadence Allegro PCB Editor. Topics Covered : (00:00) Introduction to SKILL Forms (00:19) Creating the Form Definition File (01:38) Defining Form Size and Layout"
YouTube Link 2025-03-03T16:39Z 40.6K followers, [---] engagements
"GLOBALFOUNDRIES ASIC Design Team Validates Hierarchical Test Architecture with Cadence Test Solution GLOBALFOUNDRIES needed to create a hierarchical test methodology for highly-complex custom ASICs. The challenge was to be able to seamlessly migrate the architecture without design or compute overhead. The Cadence test solution enabled the team to develop such a methodology and reduce significantly both the memory and CPU usage"
YouTube Link 2016-11-07T19:26Z 40.7K followers, [---] engagements
"What's New in Voltus IC Power Integrity Solution - SSV [-----] In this video you will learn about the key Voltus IC Power Integrity Solution features implemented in the SSV [-----] release. #LearnWithCadence #EDA #Voltus Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic"
YouTube Link 2023-05-16T20:42Z 40.7K followers, [---] engagements
"AI Driven Data Analytics Improving Design Team Productivity Dr Venkat Thanvantri VP of AI R&D at Cadence explains why AI driven data analytics enables design teams to deliver better chips more quickly by efficiently utilizing the vast quantities of valuable EDA data that is being generated. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:"
YouTube Link 2022-09-13T14:15Z 40.7K followers, [---] engagements
"What Is Multibit Cell Inference MBCI This video explains the concept of multibit cell inference for design optimization and it's benefits in synthesis. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon more than 30"
YouTube Link 2024-03-19T15:58Z 40.7K followers, [---] engagements
"My VisionBoard: Ian Dennison Cadence Design Systems Ian Dennison Solutions Group Director Custom IC Group at Cadence talks about his personal vision board and the exciting innovations he sees taking place in AI as well as Cadence's contributions to these developments. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:"
YouTube Link 2018-06-12T13:39Z 40.7K followers, [---] engagements
"How Alphawave Semi Uses Cadence Tools for High-Speed Connectivity Design Alphawave Semi delivers industry-leading high-speed connectivity solutions for AI data centers 5G wireless infrastructure autonomous vehicles and storage systems. Their cutting-edge technology enables wired connectivity that is faster more reliable and lower power meeting the demands of next-generation applications. The challenge Completing complex designs under tight schedules without compromising quality. But to overcome these hurdles Alphawave Semi relies on Cadence tools including : Clarity 3D Solver and Clarity"
YouTube Link 2025-08-15T22:24Z 40.6K followers, [---] engagements
"Revolutionizing Chip Design & Verification with Cadence AI Innovations Hear from Ziyad Hanna Corporate Vice President at Cadence as he unveils groundbreaking AI advancements in the verification domain. Learn about Verisium Cadence's cutting-edge AI solution transforming verification with smart bug localization efficient coverage closure and formal verification technologies. Discover how Sim.AI accelerates coverage closure by over 5X and how Jasper Proof Master significantly boosts formal verification productivity. This video also showcases the Cadence Jedi platform designed to propel"
YouTube Link 2025-01-09T01:00Z 40.6K followers, [---] engagements
"What Are Gate Array Cells ECO Flow Explained with Cadence Tools What are Gate Array Cells and why are they important in ECO Gate array cells are physical-only cells used during Engineering Change Orders (ECO). A base gate array cell acts like a filler cell and can be replaced with a logical gate array cell during ECO without impacting the base layers. In this video youll learn : What are gate array filler cells How they enable post-mask ECO Why size and symmetry matter for easy swapping Example: replacing filler cells with multiple logical cells Timestamps: (00:00) Introduction to gate array"
YouTube Link 2025-09-17T18:59Z 40.6K followers, [---] engagements
"Introducing Cadence HiFi 5s Cache-Coherent Multicore DSP for Next-Gen Audio Audio and voice applications are evolving rapidly across automotive infotainment TVs soundbars PCs earbuds and AR/VR devices. These use cases demand AI processing at the edge object-oriented audio codecs and software-defined vehicles making multicore DSP architectures essential. In this video Prakash Paradapati Marketing Director for Audio DSPs at Cadence introduces the cache-coherent HiFi 5s symmetric multiprocessor a groundbreaking solution that simplifies multicore software development by ensuring hardware-level"
YouTube Link 2025-06-20T15:44Z 40.6K followers, [---] engagements
"What Happens to Nets When the VLSI Router Detects Noise #cadence #computereducation VLSI routing tools use real time Signal Integrity (SI) analysis to detect glitches crosstalk and aggressorvictim coupling. This video explains how SI aware routing improves signal integrity by balancing signal integrity timing and routability. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram:"
YouTube Link 2026-02-06T10:15Z 40.8K followers, [---] engagements
"Explore How Samsung SARC Achieved 4X Productivity with Cadence Cerebrus AI Studio Discover how the Samsung Austin Research and Development Center (SARC) unlocked 4X productivity using Cadence Cerebrus AI Studio a breakthrough in AI-driven chip design. In this short but powerful video Alex Spencer Principal Engineer at SARC shares how his team accelerated semiconductor design workflows optimized multiple designs in parallel and enhanced efficiency in high-performance computing (HPC) systems. Cadence Cerebrus AI Studio is transforming the future of EDA (Electronic Design Automation) by enabling"
YouTube Link 2025-05-07T17:00Z 40.6K followers, [----] engagements
"CadenceCONNECT Photonics/Quantum Summit: Driving Innovation in Photonic Design Hear from Gal Jongbloet PhD researcher at IDLab (Ghent University imec) as he shares his experience using Cadence Photonics solutions for designing high-speed electro-optical transceivers and reflects on the value of attending the #CadenceCONNECT Photonics/Quantum Summit. Discover how Cadence tools empower photonic design with adaptable models and how the summit fosters collaboration across photonics quantum computing and optical innovation. Key Topics Covered🔍 Why Cadence tools are essential for photonic design"
YouTube Link 2025-11-12T21:49Z 40.7K followers, [--] engagements
"Celtro Is Making Medical Implants Battery-Free Using Cadence Tools Learn how Celtro develops battery-free medical implants using Cadence tools to harvest energy from the human body reducing pacemaker size and surgery risks. This technical spotlight provides Biomedical Engineers and Low-Power Chip Designers with a blueprint for disrupting the MedTech industry by replacing chemical batteries with biological energy harvesting. The Evolution of Bio-Electronic Energy Harvesting In the world of Intelligent System Design the most significant constraint for Medical Implants has always been the"
YouTube Link 2026-01-06T20:58Z 40.8K followers, [---] engagements
"Butterfly Network Puts Ultrasound on a Chip with Cadence Learn how Butterfly Network used Cadence System Design and Analysis technology to create the worlds first 3D ultrasound imaging system that can be carried in your pocket. #Cadence #3dultrasound #technology Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence"
YouTube Link 2022-10-12T16:28Z 40.7K followers, [----] engagements
"Glitch and Crosstalk Noise in VLSI: Explained in [--] seconds #cadence #pcbdesign #eda This 60-second video describes how glitch and crosstalkthe two primary noise mechanisms in routed designsimpact signal integrity and timing. Glitches can induce functional failures when spikes propagate through nets while crosstalk can create setup or hold timing violations. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram:"
YouTube Link 2026-02-04T15:30Z 40.8K followers, [----] engagements
"Cadence UCIe Chiplet IP Complete Solution for Multi-Chiplet Design & Verification As high-performance computing (HPC) demands increase for density bandwidth and power efficiency chiplet technology is revolutionizing semiconductor design. Cadence leads this transformation with silicon-proven solutions for die-to-die connectivity advanced packaging and heterogeneous integration. This video introduces Cadences 40Gbps Ultralink solution for 2D standard packages and the Universal Chiplet Interconnect Express (UCIe) ecosystem enabling plug-and-play chiplet integration across diverse dies and"
YouTube Link 2025-05-20T18:50Z 40.6K followers, [---] engagements
"100X Faster Chips: Built with Cadence Tools Neurophos is an AI accelerator chip company thats pioneering a new era of optical computing. Its building optical computing chips that are 100X faster and 100X more energy efficient than todays best GPUs. This breakthrough began with an ambitious goalto shrink the optical transistor by 10000X. To push silicon photonics to a whole new level Neurophos is using Cadences Virtuoso Studio EMX Planar 3D Solver Spectre RF Option and Quantus Extraction Solution."
YouTube Link 2026-02-05T01:08Z 40.8K followers, [---] engagements
"What is Clock Skew in VLSI Design #microsoft #tech #dataanalytics Clock skew is a critical concept in synchronous digital circuits influencing timing closure and overall chip performance. In this video we explain what clock skew is why it occurs and the different types - positive skew negative skew and zero skew - with their impact on setup and hold timing. Clock skew refers to the difference in arrival times of the clock signal at different sequential elements like flip-flops. Ideally the clock should reach all points simultaneously but physical factors such as wire delays and routing"
YouTube Link 2026-01-30T05:00Z 40.8K followers, [---] engagements
"New Cadence Allegro Platform Accelerates Design of Compact High-Performance Products Hemant Shah from the Allegro PCB unit at Cadence introduces the launch of the new Allegro platform 17.2-2016 at CDNLive EMEA [----] Cadence European user conference. In this video you will hear about the key enhancements in the new portfolio. For more information on the Allegro technology portfolio please visit www.cadence.com/news/allegro172 cadence allegro PCB CDNS flex design rigid-flex design cadence allegro PCB CDNS flex design rigid-flex design"
YouTube Link 2016-06-07T14:28Z 40.7K followers, [---] engagements
"Announcing Celsius Thermal Solver a new approach to system-level thermal analysis In this week's Whiteboard Wednesdays video Be Gu introduces Celsius Thermal Solver a new tool employing finite element analysis (FEA) techniques for thermal analysis of electronic systems. Ben explains how a novel architecture enables Celsius to deliver 10x capacity and performance improvements over existing solutions. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook:"
YouTube Link 2019-09-18T03:59Z 40.6K followers, [----] engagements
"Cadence Introduces the Janus NoC System IP As Cadence System Solution Group expands its capabilities to become a system design partner the new addition of the Cadence Janus Network on Chip to the IP portfolio aims to ease system integration and improve time to market. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:"
YouTube Link 2024-08-05T21:22Z 40.6K followers, [----] engagements
"How @SumitomoElectric Uses Cadence AWR to Design Wideband Amplifiers for Base Stations Sumitomo Electric Industries is pushing the boundaries of microwave amplifier design for shared base stations addressing critical challenges like lower cost reduced footprint and high efficiency. In this video learn how Sumitomo engineers developed a wideband amplifier architecture (MBRA) introduced in [----] designed to deliver micro-efficiency and support next-generation wireless networks. This innovation is essential for achieving shared base station deployments enabling operators to optimize"
YouTube Link 2025-08-27T19:59Z 40.6K followers, [---] engagements
"How @VoxelSensors Uses Cadence Tools to Build Next-Gen AI Perception Systems The future of intelligent machines starts with intelligent perception and VoxelSensors is leading the way. Todays perception systems are power-hungry slow and fail in real-world conditions like dust fog or rain. They also generate massive amounts of data that processors cant handle resulting in wasted resources and poor user experiences for AR glasses smart assistants and robots. VoxelSensors has cracked the code with its unique sensing software platform delivering : 10x improvement in power consumption for all-day"
YouTube Link 2025-09-02T22:49Z 40.7K followers, [---] engagements
"NeoLogic Breaks the Limits of CMOS Design with Cadence Tools Discover how NeoLogic uses CMOS+ design and Cadence Innovus to deliver power-efficient AI server CPUs for data centers while optimizing PPA and RTL synthesis. Disrupting Modern CPU Architecture NeoLogic is redefining the semiconductor landscape with its proprietary CMOS+ design technology. By focusing on reducing the complexity of microprocessors rather than just transistor scaling NeoLogic delivers superior power-efficient server CPUs for modern data centers. This innovation integrates seamlessly with the standard CMOS fabrication"
YouTube Link 2025-12-23T17:16Z 40.8K followers, [---] engagements
"Cadence Design Systems: SEMICON West [----] SEMICON West [----] in San Francisco This is a big event with an amazing opportunity to meet those who connect the electronic systems design community to the electronics supply chain. Cadence booth #2135 to learn about their new design techniques including: large-scale analog verification simulation RF and RFIC module co-design integrated electronics/photonic design automation advanced IC packaging and cross-platform solutions and of course designing in the cloud Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsSQ"
YouTube Link 2019-07-09T18:46Z 40.7K followers, [---] engagements
"Headphone Spatialization on Tensilica Hi-Fi DSP Cadence & Fraunhofer Demo Master headphone spatialization on Tensilica Hi-Fi DSP. Learn how Fraunhofer & Timbrey Labs optimize 3D audio & real-time algorithm development. This technical deep-dive is designed for Audio SoC Architects and Signal Processing Engineers who need to implement immersive low-latency Headphone Spatialization and Microphone Enhancement in consumer electronics. As [----] standards shift toward personalized spatial audio understanding the integration of Fraunhofer IIS logic onto the Hi-Fi DSP is critical for maintaining"
YouTube Link 2025-02-13T04:27Z 40.6K followers, [---] engagements
"Cadences Insight into Design Process Helps the US Technology Leadership Council Achieve its Goals Find out from Dr. Eric Haseltine Chairman of the US Technology Leadership Council how Cadence brings a unique perspective on designing microelectronics and other systems to the government and how it is helping the US technology and leadership councils goal to promote better understanding between defenseintelligence contractors and the government counterparts. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect"
YouTube Link 2020-01-28T18:23Z 40.7K followers, [---] engagements
"Why Placement Blockages and Halos Matter in VLSI PnR #cadence #pcbdesign #eda Placement blockages are used to reduce local congestion and prevent detour routing that can degrade timing. Halos act as movable blockages around macros for pin accessibility and avoid placing cells too close to macro pins. Together they help achieve cleaner routing with improved timing and less local congestion. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X:"
YouTube Link 2026-02-02T03:09Z 40.8K followers, [---] engagements
"FMEDA for Automotive Safety (Optimize Designs with Cadence MIDAS Platform) Failure Mode Effect and Diagnostic Analysis (FMEDA) is essential for achieving ISO [-----] compliance in automotive systems. Cadences MIDAS Safety Platform delivers a holistic FMEDA-driven methodology integrating safety analysis verification and implementation for analog digital and mixed-signal designs. MIDAS supports two FMEDA modes : Architectural FMEDA for early design phases without detailed data based on estimated failure rates. Detailed FMEDA leveraging actual design hierarchy area gates and flops for accurate"
YouTube Link 2025-05-20T18:47Z 40.6K followers, [--] engagements
"Delivering better PPA and chip design productivity using Cadence Cerebrus Intelligent Chip Explorer Rod Metcalfe ML Product Manager explains how Cadence Cerebrus Intelligent Chip Explorer has enabled a revolution in chip design productivity allowing engineering teams to implement increasingly large and complex system on chips required by the latest 5G autonomous driving hyperscale compute industrial IoT driven products. Cerebrus the Future of Intelligent Chip Design. Find more great content from Cadence: Subscribe to our YouTube channel:"
YouTube Link 2021-07-22T12:45Z 40.7K followers, [----] engagements
"3DGS Makes Electrical Circuits in Glass Using AWR and OnCloud Learn about how 3DGS scalable process for dynamically sculpting photosensitive glass empowers high-performance electronics using Cadence AWR and OnCloud. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic"
YouTube Link 2022-07-27T16:51Z 40.6K followers, [---] engagements
"Cadence RF/Microwave Design at IMS [----] Visit Cadence at the International Microwave Symposium (IMS) to learn about the latest solutions for RF-to-mmWave component and system design including innovations in circuit simulation electromagnetic (EM) thermal analysis and implementation flows across RFICs/MMICs packages/modules and PCBs. Cadence experts demonstrate new features in the AWR Design Environment platform and the advantages of integration with Cadences Clarity 3D Solver Celsius Thermal Solver and EMX Planar 3D Solver as well as the benefits of the benefits of the Virtuoso RF Solution."
YouTube Link 2023-06-05T16:45Z 40.6K followers, [---] engagements
"Why Chiplets Are the Future of SoC Design Chiplet-based SoC architectures are transforming semiconductor design delivering cost efficiency customization configurability and ecosystem scalability. This presentation explores Cadences chiplet reference platform enabling faster time-to-market and modular system design for automotive robotics aerospace and defense applications. Learn how ARM CSA UCIe and Cadence tools simplify integration while ensuring security and functional safety. Key Highlights : Industry shift : From monolithic SoCs to modular chiplets to overcome reticle limits cost and"
YouTube Link 2025-03-25T17:43Z 40.6K followers, [---] engagements
"Equal1 Builds the Worlds First Silicon-Based Quantum Computer with Cadence Tools Equal1 is pioneering the worlds first silicon-based quantum computer integrating the Quantum Processing Unit (QPU) and control electronics on a single chip. This breakthrough design operates at [--] Kelvin colder than space and dramatically reduces size wiring and power from [---] MW to just [--] kW making quantum computing practical and scalable. Why Quantum Matters : It matters because Quantum computers use qubits instead of bits enabling exponential compute power for challenges like drug discovery battery material"
YouTube Link 2025-04-08T15:50Z 40.7K followers, [---] engagements
"Fujitsu Designing the Worlds Leading Innovations with Cadence Intelligent System Design Fugaku the worlds most powerful supercomputer designed with Cadence by Fujitsu. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables electronic systems and semiconductor companies to create the"
YouTube Link 2020-10-14T18:15Z 40.7K followers, [----] engagements
"Faster Timing Signoff with Tempus ECO: Fix Violations & Optimize Power Tempus ECO is a powerful feature in Cadence Tempus Timing Signoff Solution designed to accelerate signoff closure while delivering the best PPA (Power Performance Area) in the industry. In this video learn how Tempus ECO helps designers fix timing violations reduce power consumption and achieve convergence on large complex designs. Tempus ECO offers : 50% faster time-to-signoff closure 2x faster STA performance with DSTA and CMMC Highly robust ECO flow for cleaning up remaining timing violations with minimal iterations"
YouTube Link 2025-11-20T04:16Z 40.6K followers, [---] engagements
"What is Electromigration and IR Drop Analysis This video introduces Electromigration (EM) and IR drop. EM refers to the unwanted movement of materials in a semiconductor. IR drop refers to the voltage drop on metal wires during current flow due to the resistance of metal wires. For more information about Quantus-Tier3 course visit: https://www.cadence.com/en_US/home/training/all-courses/86150.html For more related videos visit https://support.cadence.com/TrainingBytes/QRC (Cadence login required). #learnwithcadence #eda #CadenceQuantus #RLCK Connect with Cadence: Website:"
YouTube Link 2024-04-18T14:32Z 40.7K followers, 11.7K engagements
"Cadence ASK AI Assistant (Faster Debug & Smarter Support with GenAI) Meet Cadence ASK AI Assistant your Generative AI-powered troubleshooting companion designed for designers and engineers. ASK AI revolutionizes learning and support by analyzing vast knowledge bases and delivering context-specific insights in seconds. Why ASK AI matters [--]. Instant troubleshooting: Quickly identify root causes and resolve issues faster. [--]. Smart summarization: Condenses complex debugging and learning collateral into actionable answers. [--]. 24/7 access: Available via ASK Portal homepage or interactive chatbot."
YouTube Link 2025-09-25T04:03Z 40.6K followers, [---] engagements
"What Is DFT in VLSI Design In this 1-minute video you will understand the concept of DFT (Design for Test). Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon more than [--] years of computational software expertise. The"
YouTube Link 2024-07-24T18:09Z 40.7K followers, [----] engagements
"TSMC & Cadence Announce N2P A16 and A14 Advancements at Tech Symposium At the recent TSMC Technology Symposium groundbreaking innovations were unveiled to accelerate AI transformation faster computing and greater power efficiency. Hear from Lluis Paris Senior Director at TSMC North America as he shares details on design tool certifications for N2P A16 with Super Power Rail and N3C process plus collaboration on A14 technology a major leap from the industry-leading N2 nanosheet transistor technology. This partnership between TSMC and Cadence reflects a shared commitment to technology scaling"
YouTube Link 2025-06-19T14:38Z 40.6K followers, [---] engagements
"Voltus Insight AI: Cadences Generative AI Solution for IR Drop Fixes Voltus Insight AI is Cadences AI-driven in-design solution for improving chip power integrity. This video explains how this generative AI technology predicts IR drop issues early and enables timing and DRC-aware fixes across placement power grid reinforcement routing and ECO stages. Youll learn about its four key features : Fast IR inferencing engine: Uses proprietary neural networks for instant feedback on design changes IR drop diagnostics: Deep learning identifies aggressors victims and resistance bottlenecks Multimethod"
YouTube Link 2025-11-26T09:55Z 40.7K followers, [---] engagements
"Cadence HBM3E PHY @14.4Gbps Cadence HBM3E PHY IP sets the benchmark for high-speed memory interfaces. In this demo our engineers showcase the performance and robustness of the PHY operating at 14.4Gbps TX speed while reading/writing to the HBM3 stack at 10.4Gbps DRAM speed. Key highlights : Aggressive PPA targets for 3nm technology node Robust TX eye diagram with 110mV eye height and 70ps width Loopback mode validation with error-free operation Demonstration of 1D timing margins and 2D eye captures for memory reads Future-proof design for higher DRAM speed grades Why it matters : Higher"
YouTube Link 2025-10-22T14:13Z 40.7K followers, [---] engagements
"The Cadence Digital Full-Flow for SoC Design and Implementation Designs are only getting bigger and more complex and your PPA targets are harder to meet every project. You want a complete design and implementation solution that produces the best PPA in the shortest possible time. This can only be achieved with the Cadence digital full-flow. From Genus synthesis to Innovus layout and Tempus and Voltus signoff with common timing and power engines in the only tight integration of layout timing and voltage signoff tools for superior convergence. Cadence computational software for intelligent"
YouTube Link 2020-07-10T17:57Z 40.7K followers, [----] engagements
"Stop Repeating ECOs: Repair with Master/Clone Aware Timing Optimization #cadence #pcbdesign #eda In this video discover how Master Clone aware timing optimization lets you fix timing once and automatically apply the repair across every replicated core in a hierarchical chip design. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/"
YouTube Link 2026-02-03T10:13Z 40.8K followers, [---] engagements
"Sequans Designs its Future 5G IoT Platform Using Virtuoso RF Solution Learn how Sequans develops its next generation 5G Internet of Things (IoT) platform using Virtuoso RF Solution the comprehensive full-suite solution from Cadence. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence Cadence enables"
YouTube Link 2021-11-12T18:39Z 40.7K followers, [---] engagements
"Enhancing Power Grid Reliability with Early Rail Analysis (ERA) #cadence #pcbdesign #eda This video introduces Early Rail Analysis (ERA) a methodology used to evaluate powergrid integrity early in the physical design flow. ERA helps designers identify and fix powergrid issues before routing is complete reducing latestage design risks. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram:"
YouTube Link 2026-02-02T10:54Z 40.8K followers, [---] engagements
"Samsung & Cadence Partner to Deliver 4nm AI Chip with 1.6B Instances & 22% Power Savings Samsung has achieved a major milestone in semiconductor innovation successfully taping out a multi-billion-instance 4nm AI chip powered by Cadences advanced signoff solutions. This breakthrough demonstrates how cutting-edge EDA tools and strategic collaboration can accelerate design closure optimize power and meet aggressive tape-out schedules. In this video discover how Samsung leveraged Cadence Tempus Timing Signoff Certus Closure and distributed STA technology to overcome the challenges of designing"
YouTube Link 2025-05-02T19:03Z 40.6K followers, [---] engagements
"Neurophos Is Reinventing Optical Computing with the Help of Cadence Tools Neurophos is an AI accelerator chip company thats pioneering a new era of optical computing. Its building optical computing chips that are 100X faster and 100X more energy efficient than todays best GPUs. This breakthrough began with an ambitious goalto shrink the optical transistor by 10000X. To push silicon photonics to a whole new level Neurophos is using Cadences Virtuoso Studio EMX Planar 3D Solver Spectre RF Option and Quantus Extraction Solution."
YouTube Link 2026-02-04T17:02Z 40.8K followers, [---] engagements
"PA Design with Cadence Virtuoso PDK in Microwave Office and Tower Semis SiGe BiCMOS Technologies Learn how you can accelerate your power amplifier (PA) design using a Virtuoso PDK with Tower Semiconductor's SiGE BiCMOS technology within the Microwave Office design environment. Learn more about Microwave Office software. https://www.cadence.com/en_US/home/tools/system-analysis/rf-microwave-design/awr-microwave-office.htmlutm_source=youtube&utm_medium=video&utm_campaign=pdk&utm_term=07-22 Start a free trial today."
YouTube Link 2022-08-03T18:14Z 40.6K followers, [----] engagements
"My VisionBoard: Robert Schweiger Cadence Design Systems Robert Schweiger Director Product Marketing Automotive at Cadence talks about his personal vision board and the exciting innovations he sees in the automotive industry as well as Cadence's contributions to these developments. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter:"
YouTube Link 2018-04-19T09:01Z 40.7K followers, [---] engagements
"Ambarella's Edge AI Breakthrough: Powered by @Samsung Foundry and @cadencedesignsystems The future of AI is real-time secure and scalable and that future is Edge AI. In this video discover how Ambarella in partnership with Samsung Foundry and Cadence is redefining AI performance with its latest Edge AI SoC the N1655i. This breakthrough solution delivers industry-leading AI performance per watt enabling real-time decisions at the point of data capture. With the ability to process LLMs and VLMs up to [--] billion parameters while decoding [--] streams of 1080p video at just [--] watts the N1655i sets"
YouTube Link 2025-09-05T18:22Z 40.7K followers, [---] engagements
"Hailo [--] AI Vision Processor with Cadence Vision P6 DSP CES [----] Demo Discover the Hailo [--] AI Vision Processor. Learn how Cadence Vision P6 DSP enables real-time object detection and image pre-processing for Edge AI at CES [----]. This technical deep-dive is designed for SoC Architects and Embedded AI Engineers who need to implement high-performance Real-time Object Detection in power-constrained environments. As [----] standards for smart cities and autonomous driving demand higher efficiency understanding the role of the Vision P6 DSP in the Hailo [--] ecosystem is critical for optimizing"
YouTube Link 2025-02-13T04:26Z 40.6K followers, [---] engagements
"embedded world 2024: Using Low-Power DSPs for In-Cabin Sensing With the advancement of cabin comfort tied into active safety the need for accurate passenger detection localization size (child vs. adult vs. pet) and monitoring (fatigue vital signs road focus) are getting tied up with the advanced driving assist functions of a vehicle to operate safely and provide a great user experience inside the cabin. So it is crucial that the various types of sensors work together within the cabin. RGB-IR + short-range radar + time of flight are some of the upcoming sensing modalities that are penetrating"
YouTube Link 2024-05-28T18:44Z 40.6K followers, [---] engagements
"The Future of Quantum Computing is Here (with Cadence) Hear from Pouya Dianat PhD Chief Revenue Officer at @QCiQuantumComputingInc as he shares how his team collaborates with Cadence to bring thin-film photonic foundry services and PDK solutions to a broader market. Discover how Cadence tools accelerate product development enable market deployment and foster innovation in photonics and quantum computing. The #CadenceCONNECT Photonics/Quantum Summit is more than an eventits a hub for networking knowledge sharing and exploring cutting-edge technologies beyond the status quo. Pouya explains why"
YouTube Link 2025-11-13T15:03Z 40.6K followers, [---] engagements
"Whiteboard Wednesdays - 3X Faster Design Closure with Quantus Integrated Virtual Metal Fill In this week's Whiteboard Wednesdays video Senior Product Engineering Manager Varun Raj Garapati outlines why traditional metal fill insertion usually at the signoff stage is not recommended for FinFET designs to ensure fastest design closure. The Quantus Integrated Virtual Metal Fill (IVMF) solution offers designers the ability to run virtual metal fill much earlier in the design during post-route optimization stage to reduce ECOs for faster design closure. IVMF functionality is available both"
YouTube Link 2019-03-27T19:16Z 40.7K followers, [----] engagements
"What is an ECO What are challenges of doing a manual ECO Engineering Change Orders (ECOs) are a critical part of the digital design flow especially when last-minute bug fixes or design updates are needed. In this video we explain the difference between manual ECO and conformal ECO and how metal-only ECOs using spare cells or gate arrays can accelerate implementation while minimizing cost and risk. Learn how Conformal ECO helps automate complex changes reduce iterations and ensure timing and DRC compliance especially for large ECOs that are difficult to manage manually. Key Topics Covered :"
YouTube Link 2025-11-06T05:34Z 40.6K followers, [---] engagements
"Socionext Is Tackling Large-Scale SoC Designs with Cadence Certus Quantus and Tempus Solutions Socionext is an SoC company that has pioneered its business model to help companies achieve differentiation according to their specific needs. They collaborate closely with their partners worldwide and deliver complete SoC solutions from system design to production quality and control. In advanced technology nodes such as 5nm and 3nm billion-gate full-chip designs face prolonged runtimes and substantial memory usage leading to diminished productivity. To combat these large-scale design challenges"
YouTube Link 2024-05-21T21:58Z 40.7K followers, [---] engagements
"Cadence Showcases First-Pass Silicon Success for 32GT/s UCIe Gen2 IP Step inside Cadences post-silicon validation lab as we showcase the first-pass silicon success of our 32GT/s UCIe Gen2 IP. This demonstration highlights wide-open receiver eyes error-free performance and fully hardware-based bring-up for rapid validation and simplified integration. Key features include : Two UCIe links tested across 7.4mm and 25mm channels (maximum reach per UCIe spec). Automatic LTSSM training flow handled by FI RTL no external firmware or scripts required. Internal impedance calibration without external"
YouTube Link 2025-08-05T14:01Z 40.6K followers, [---] engagements
"A day in the life as an HR intern at Cadence Ever wondered what it's like to work at a top tech company 👩💻✨ Come spend a day with our HR Intern From coordinating All Hands meetings to drafting internal communications see why Cadence is certified as a Great Place to Work. Its not just about chips and software; its about the people Join Us: Ready to start your journey Check out our careers page ------------------------------------------------------------------------------------------------------------------------------------------------------------------ Connect with Cadence : YouTube:"
YouTube Link 2025-09-11T19:20Z 40.7K followers, [----] engagements
"My VisionBoard: Steven Lewis Cadence Design Systems Steven Lewis Product Marketing Director at Cadence talks about his personal vision board and the exciting innovations he sees for the future and how Cadences analog division can enable these innovations. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About"
YouTube Link 2018-06-12T07:14Z 40.7K followers, [---] engagements
"How New DFT Solution Trims Test Time for Digital Logic Hear Paul Cunningham VP of R&D at Cadence explain how the company's new Modus Test Solution reduces test time for digital logic by up to 3X compared to other available solutionswithout impacting chip size or yield. After watching the video learn more about the Modus Test Solution here: http://bit.ly/1Skbda1"
YouTube Link 2016-02-02T18:31Z 40.7K followers, [----] engagements
"What is Hold Slack in VLSI Design #cadence #pcbdesign #eda Understanding hold slack is essential for timing closure in any VLSI design. In this video youll learn what hold slack truly means why it occurs and how it impacts real chip sign off. I walk through the hold slack formula explain why it is independent of clock frequency and demonstrate a real STA timing report so you can confidently read Required Time Arrival Time and Slack values. Whether youre preparing for STA interviews or working on timing closure in physical design this video gives you clear intuition practical demos and a solid"
YouTube Link 2026-02-02T06:57Z 40.8K followers, [----] engagements
"Cadence Digital Badge: Flaunt Your Expertise With Cadence Digital Badge Watch this video to explore Cadence Digital Badges and how you can flaunt one The exams can be taken from Training Courses (www.cadence.com) https://support.cadence.com/apex/CosLms_DoceboPagedeeplink=/pages/18/all-courses. Log in to support.cadence.com and search for the desired course or Badge Exam. Find More Information: Check out the currently available certification courses and get information. https://www.cadence.com/content/cadence-www/global/en_US/home/training/become-cadence-certified.html Get a Cadence Digital"
YouTube Link 2022-05-23T14:26Z 40.7K followers, [----] engagements
"CadenceLIVE Silicon Valley [----] Thanks to all who joined us at #CadenceLIVE Silicon Valley for [--] days of exciting keynotes [--] tracks of technical sessions a busy Designer Expo and a test drive in a Formula [--] #McLaren simulator. In case you missed it the technical sessions will be available on-demand soon. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn:"
YouTube Link 2023-05-03T15:55Z 40.7K followers, [---] engagements
"What Is a Level Shifter Master the physical implementation of Level Shifters. Learn about dual-rail power connections placement constraints and how to optimize timing delays across voltage islands. Physical Design Constraints Level Shifters are not just logical elements; they impose specific physical constraints on the P&R flow. Secondary Power Rails: Since a level shifter needs to "see" both voltages routing can be complex. You often encounter "Multi-row" or "Separate" connection types where the cell needs access to a backup power grid. Placement Strategy: You cannot place a level shifter"
YouTube Link 2025-02-20T17:45Z 40.6K followers, [---] engagements
"EW 2022: Cadence Tensilica Vision and AI DSP IP Showcased in ADAS Application In this video from Embedded World [----] Amol Borkar demonstrates advanced driver assistance system (ADAS) and 360-degree surround view functions on an Automotive AI Perception Processor from Black Sesame Technologies. The Black Sesame Technologies' A1000 SoC features [--] Tensilica Vision P6 DSPs along with Black Sesame Technologies' own Ultra Deep Learning Neural Network hardware accelerator. Leveraging these two IP the SoC is able to very efficiently perform pedestrian detection street sign detection lane detection"
YouTube Link 2022-08-04T17:32Z 40.7K followers, [---] engagements
"Quantus I-DSPF Output Demo Series: Episode [--] (P2P Analysis and Parasitic Visualization) Welcome and welcome back the Quantus DSPF Interactive Output (Quantus I-DSPF Output) Demo Series a five-part exploration of the innovative circuit debugging tool. This series highlights the interactive features seamlessly integrated with Virtuoso Studio to revolutionize the design debugging process for faster design closure. Join us for episode four of the Quantus I-DSPF Demo Series where presenter Raksha Jain covers Quantus resistance and analysis as well parasitic visualization using Quantus I-DSPF"
YouTube Link 2024-05-29T18:49Z 40.7K followers, [---] engagements
"Anirudh Devgan and Cristiano Amon - CadenceLIVE Silicon Valley [----] - Fireside Chat Hear from #Qualcomm CEO Cristiano Amon at #CadenceLIVE Silicon Valley discussing how Qualcomms partnership with #Cadence is fundamental to creating the technologies to enable intelligent computing everywhere Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/"
YouTube Link 2024-05-01T14:43Z 40.6K followers, [----] engagements
"Explore How NepTech Drives Maritime Decarbonization with Cadence Fidelity CFD Maritime transport is vital for global trade but its also a major contributor to greenhouse gas emissions. NepTech is tackling this challenge by designing low-carbon passenger vessels and work boats integrating electric hybrid and electro-hydrogen propulsion for sustainable maritime solutions. To accelerate innovation NepTech leverages Cadence Fidelity CFD Software as its digital testing facility replicating real-world ship behavior in a virtual environment. This approach reduces computation time while maintaining"
YouTube Link 2025-03-27T19:29Z 40.6K followers, [---] engagements
"What is the Antenna Effect in VLSI Design The antenna effect is a critical challenge in VLSI physical design impacting chip reliability and yield during semiconductor manufacturing. In this video we explain what the antenna effect is why it occurs and how designers mitigate its risks using antenna rules and diodes. During fabrication steps like plasma etching long metal interconnects can accumulate charge acting like antennas. If this charge discharges into the gate oxide of transistors before they are connected to power or ground it can cause oxide breakdown and even chip failure. Learn how"
YouTube Link 2025-11-14T05:50Z 40.6K followers, [---] engagements
"My Life at Cadence Jaswinder Ahuja Meet Jaswinder Ahuja Corporate Vice President International Headquarters. Watch this Employee Spotlight interview to hear about Jaswinder's remarkable 30-plus year career at Cadence and what brings him to work every morning. Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence: Website: http://www.cadence.com Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence"
YouTube Link 2021-11-24T12:25Z 40.7K followers, [----] engagements
"Life as an Application Engineer at Cadence Dual Interview with Helga and Serge Explore the Application Engineer life at Cadence. Learn how analog design tools hardware verification and AI optimization are shaping microelectronics. This technical spotlight is designed for Electronic Engineers and System Architects evaluating professional growth in the EDA sector. In the landscape of Intelligent System Design the Application Engineer (AE) role is the bridge between complex software IP and real-world hardware success. This video provides a granular breakdown of the workflows involved in Analog"
YouTube Link 2025-02-03T15:16Z 40.7K followers, [---] engagements
"UCIe Protocol Transforming Chiplet Architecture and Verification Cadence Explore how Universal Chiplet Interconnect Express (UCIe) is revolutionizing chip architecture moving from monolithic designs to scalable systems of chiplets. This technical deep-dive is designed for SoC Architects and Verification Engineers who are navigating the transition from single-die monolithic chips to System of Chiplets. As AI and automotive demands push silicon beyond the Reticle Limit mastering the UCIe Protocol Stack is essential for maintaining performance and scalability in Intelligent System Design. The"
YouTube Link 2025-02-10T22:40Z 40.7K followers, [---] engagements
"Master Cadence ASK Portal AI-Powered Learning & Debugging Made Simple Struggling to debug design issues or learn new methodologies efficiently Discover the Cadence Learning and Support Portal your ultimate destination for AI-powered troubleshooting training resources and expert guidance available anytime anywhere. The Cadence ASK Portal combines a comprehensive knowledge base video library and Generative AI (Gen AI) capabilities to help you resolve issues faster adopt new technologies and become an advanced user of Cadence tools. Whether you need installation and licensing help product"
YouTube Link 2025-07-07T15:48Z 40.6K followers, [---] engagements
"3rd Gen AMD EPYC with V-Cache Technology Powers Cadence Computational Software Cadence and AMD collaborate to enable engineers to create the most innovative products of tomorrow. Together we provide the most powerful computational software on the highest performance processors for technical computing. AMD expands its high performance x86 server processor series for technical computing with the AMD EPYC [----] Series processors with AMD 3D V-Cache technology. And Cadences computational software is tuned to fully utilize the ample cache for large data accesses. The 3rd Gen AMD EPYC processors"
YouTube Link 2022-03-21T13:05Z 40.7K followers, [----] engagements
"How Timing Paths Work in Multi-Supply Voltage Designs #cadence #pcbdesign #eda This video explains how timing paths behave in multisupply voltage (MSV) designs focusing on power domains level shifters and crossdomain timing analysis. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook: https://www.facebook.com/CadenceDesign Twitter/X: https://twitter.com/Cadence Instagram: https://www.instagram.com/cadencedesignsystems/"
YouTube Link 2026-02-05T09:01Z 40.8K followers, [----] engagements
"LVS Debugging Thumb Rules Let's explore a few thumb rules for PVS/Pegasus LVS Debugging. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon more than [--] years of computational software expertise. The company applies its"
YouTube Link 2024-12-17T17:20Z 40.7K followers, [---] engagements
"Keep up with the USB Type-C industry with Cadence Design IP Are you prepared for the markets shift to the USB Type-C specification It appears that every USB device will be converted to the new connector to provide users the single cable experience they desire. But enabling a plug-and-play USB Type-C solution is no picnic. With data rates up to 10Gbps and up to 100W of power USB Type-C is the new connector for exciting next-generation products. Add in DisplayPort support via USB Alternate Modes (Alt Modes) and the design challenges become extremely complex. Get to market faster and with higher"
YouTube Link 2016-01-19T22:51Z 40.7K followers, [---] engagements
"Cadence CEO Dr. Anirudh Devgan appears on the Acquired podcast at @NVIDIA GTC Join Dr. Satoshi Matsuoka Pat Gelsinger and Dr. Anirudh Devgan in this deep-dive discussion from NVIDIA GTC exploring the past present and future of computing from CUDAs early gamble to AI acceleration and quantum computing breakthroughs. Key Highlights : NVIDIAs CUDA Revolution: How repurposing GPUs for general-purpose computing changed the industry. First GPU Supercomputer: Dr. Matsuokas story of building Sububame and outperforming IBMs Blue Gene. Intels Perspective: Pat Gelsinger on CPU dominance accelerated"
YouTube Link 2025-03-31T20:14Z 40.6K followers, [----] engagements
"Introducing Sigrity SPEEDEM in Layout Workbench This video demonstrates the updates and enhancements made in Sigrity SPEEDEM in the Sigrity and Systems Analysis [------] HF3 release. After viewing this video you will learn about: - Introduction of Sigrity SPEEDEM in Layout Workbench - Postprocessing functionalities in SPEEDEM Generator (SPDGEN) - Improved In-Tool Self Help To know more about the Sigrity products visit https://www.cadence.com/en_US/home/tools/system-analysis/signal-and-power-integrity.html #LearnWithCadence #EDA #SPEEDEM Find more great content from Cadence: Subscribe to our"
YouTube Link 2021-12-01T18:21Z 40.7K followers, [----] engagements
"Cadence Tensilica ConnX DSP 5x Faster Radar-Based Multi-Object Tracking Master radar-based multi-object tracking with Cadence Tensilica ConnX DSPs. Learn how the Kaltera Radar Sensor achieves 5x performance gains over CPUs. This technical overview is designed for Automotive Radar Architects and Signal Processing Engineers who need to implement low-latency high-precision tracking for 4D imaging radar systems in next-generation vehicles. The Evolution of Imaging Radar Processing In the complex environment of autonomous driving Radar-Based Multi-Object Tracking is critical for safety and"
YouTube Link 2025-02-13T18:15Z 40.6K followers, [---] engagements
"Explore How SJSU Spartan Racing Uses Cadence for EV Design Spartan Racing San Jose State Universitys Formula Electric SAE Team is preparing the next generation of engineers by combining classroom learning with real-world design challenges. This video showcases how Cadence Academic Network supports student innovation through industry-leading tools like Cadence Fidelity CFD for thermal and aerodynamic simulations. From brake rotor cooling analysis to heat dissipation studies Cadence solutions help students optimize performance reduce costs and accelerate design cycles. With over [---] active team"
YouTube Link 2025-05-19T17:10Z 40.6K followers, [---] engagements
"My Life at Cadence: Alessandra Nardi Software Engineering Group Director Automotive Solutions Alessandra Nardi is a software engineering group director in the Automotive Solutions Group at Cadence. She loves engineering because it provides the opportunity to build solutions. Learn about her life at Cadence and her thoughts on how great teamwork leads to success. Help us shape the future: https://www.cadence.com/en_US/home/company/careers.html Find more great content from Cadence: Subscribe to our YouTube channel: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Connect with Cadence:"
YouTube Link 2020-05-13T18:26Z 40.7K followers, [----] engagements
"What Are Aborts in Conformal Equivalence Checker Cadence Best Practices What are aborts and why do they occur during equivalence checking When comparing two designs Conformal Equivalence Checker may encounter situations where a compare point cannot be conclusively determined as equivalent or non-equivalent. These unresolved points are called aborts. In this video youll learn : What aborts are in equivalence checking Why large cones dont cares and complex logic cause aborts How runtime optimization leads to aborts Best practices to avoid aborts during RTL coding and synthesis Timestamps :"
YouTube Link 2025-09-17T19:01Z 40.6K followers, [--] engagements
"The Hidden Role of Lock Up Latches in Semiconductor Chip Design #cadence #eda #pcbdesign In this 2.5-minute video you will learn what lockup latches are why theyre essential in scan chains and how they prevent clockdomain timing violations. Learn how these transparent latches preserve scan data manage skew and ensure reliable multiclock scan shiftingall automatically handled during scan stitching by synthesis and ATPG tools. Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn: https://www.linkedin.com/company/cadence/ Facebook:"
YouTube Link 2026-01-28T03:42Z 40.8K followers, [----] engagements
"Cadence: Your Complete Solution for Disaggregated Design Success Designing high-performance disaggregated architectures for AI and HPC systems is complex. It requires silicon-proven UCIe IP robust verification and rapid signoff workflows all integrated for speed and predictability. Cadence delivers a complete solution : UCIe IP : Peer-reviewed silicon-proven for inter-die connectivity at speeds up to 64Gbps Verification IP : Accelerates coverage using UVM / System Verilog ensuring compliance with UCIe [---] and [---] standards : Integrated design & signoff : Achieve rapid closure without"
YouTube Link 2025-10-22T22:02Z 40.7K followers, [---] engagements
"Cadence PCIe [---] Demo [---] GT/s Electrical & Optical Link Performance PCIe Gen [--] is here and Cadence is leading the way In this demo Cadence engineers showcase a PCIe 7.0-compliant DUT operating at [---] GT/s PAM4 signaling on a 3nm test chip validated using a [--] GHz real-time oscilloscope. Watch as we demonstrate wide-open eye diagrams discuss Gen [--] CDR settings and highlight how performance will improve with full Gen [--] software integration. Plus see our optical link demo featuring linear pluggable optics and DR8 fiber loopback achieving an impressive pre-FEC BER of 2E-8 well below PCIe 7.0"
YouTube Link 2025-06-27T01:08Z 40.7K followers, [---] engagements
"What are DRC and LVS in Physical Verification This content describes the purpose of running DRC and LVS verification on the design. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design building upon more than [--] years of computational"
YouTube Link 2024-06-07T03:45Z 40.7K followers, [----] engagements
"Pointcloud Is Making 3D Imaging Sensors Ubiquitous Through a Single Chip Imagine a world where robots see as clearly as humans. Discover how Pointcloud is using Silicon Photonics to make 3D imaging as common as your phone camera. In the history of technology certain inventions redefine our relationship with the world. The CMOS (SIMOS) image sensor changed everything for Photography and Video making 2D imaging a part of our daily lives. Today we are standing at the threshold of a new revolution. Pointcloud is on a mission to make 3D imaging just as ubiquitous. By creating a single Chipset that"
YouTube Link 2026-01-20T20:51Z 40.8K followers, [---] engagements
"The Power of Cadence Culture Learning Diversity and Team Spirit Discover the Cadence Company Culture in Grenoble. Explore the One Team framework Engineering Career Development and global tech collaboration logic. This technical spotlight is designed for Software Architects and Hardware Engineers evaluating the long-term growth potential of a career at Cadence. In the landscape of Intelligent System Design the speed of innovation is gated by the quality of a team's synchronization. This video provides a granular look at the One Team Culture at Cadence and how it serves as a foundation for"
YouTube Link 2025-02-03T15:16Z 40.6K followers, [---] engagements
"How to Back Annotate the Schematic in the Allegro X System Capture Project Did you swap pins or rename components in your layout Don't waste time manual-typing Discover the Allegro X back annotation flow to sync your design instantly. In the fast-paced world of hardware engineering the journey from schematic to board is rarely a straight line. Often during the PCB layout phase an engineer realizes that a pin swap or a component rename is necessary to optimize routing. In traditional workflows manually bringing those changes back to the drawing board is a recipe for error. At Cadence we"
YouTube Link 2025-01-27T18:17Z 40.6K followers, [---] engagements
""Build it Right the First Time" Cadence at Paris Air Show In this talk given at the Paris Air Show James Chew from Cadence talks about the how the Test and Evaluate Before You Fabricate product development methodology once exclusive to semiconductors is now becoming increasingly more relevant to the aerospace industry. James presents the benchmark suite of Cadence tools that allows companies to be the first to market with gotta have aerospace products and systems. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html"
YouTube Link 2025-06-26T15:40Z 39.8K followers, [---] engagements
"Your Semiconductor Chips Aren't Safe: The Hidden Attack Surfaces Nobody Talks About #cadence #eda In this 1-minute video you will get a quick overview of attack surfaces and vulnerability types in the EDA flow. This training byte breaks down logic digital and analog/mixedsignal attack vectorscovering sequence manipulation sidechannels Trojan insertion fault injection timing/power/thermal exploits and glitch/RFbased attacks. Perfect for understanding how diverse hardware threats emerge across design layers and why securing silicon requires a multidimensional approach. Connect with Cadence :"
YouTube Link 2026-01-23T11:45Z 40.8K followers, [---] engagements
"Cadence Employee Spotlight: Lady Payan Cepeda Introducing Lady Payan Cepeda a Cadence Intern based in our Cambridge office. In this employee spotlight Lady discusses what inspired her to pursue a technical degree how she believes her internship at Cadence will impact her career and offers invaluable advice to students starting their studies. Click the link in our bio to check out the full video 📽 Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q"
YouTube Link 2025-02-17T17:22Z 36.5K followers, [--] engagements
"Sunday Brunch 11th October Find more great content from Cadence: https://www.cadence.com/ https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes Paul McLellan serves up blogs for the week with the latest cutting-edge technology available at Cadence Design Systems. ************************************************ Monday: Jasper User Group [----] Preview Tuesday: Innovus Mixed Placer Wednesday: TSMC OIP: Rent's Rule and Fast SerDes IP Thursday: Bessemer Ventures: The Memos That Didn't Get Away Friday: Optimized Digital Design Implementation and Signoff on TSMC N3 Featured Post: We Have"
YouTube Link 2020-10-11T07:00Z 39.9K followers, [---] engagements
"Cadence CFD Simulations Are a Key Plank in EV Maritimes Design Validation Process Auckland New Zealands EV Maritime is not just developing high-performance electric boats they are looking to help cities transform their transport systems providing cleaner and more efficient mass transit options to help us all out of our private vehicles and into active and public transport. These days computational fluid dynamics (CFD) simulation is the fastest most accurate and most powerful tool to explore design variations for efficient hull shapes. EV Maritime chose Cadence for their CFD simulations"
YouTube Link 2022-12-09T22:23Z 39.9K followers, [----] engagements
"What Is Dynamic Pattern Fault Static testing isn't enough 🛑 A "Dynamic Pattern Fault" models defects that only appear under specific timing conditions or sequences. Unlike a simple "Stuck-at" fault this requires defining Initial Values + Propagated Values to catch complex issues like Cross-Talk and Shorted Nets. ------------------------------------------------------------------------------------------------------------------------------------------------------------------ Connect with Cadence : YouTube: https://www.youtube.com/@cadencedesignsystems LinkedIn:"
YouTube Link 2025-12-18T06:52Z 40.5K followers, [---] engagements
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