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[@satnam6502](/creator/twitter/satnam6502)
"I've given up trying to get the Xilinx AMD Vivado FPGA design software running on my new MacBook Pro. I tried to use Parallels with Rosetta (Linux ARM64 running AMD64 Vivado) and UTM with QEMU emulation (Linux AMD64) but neither approach seems to work to produce a stable experience e.g. synthesis almost works but then some random thing crashes. It would be wonderful if AMD produced Vivado ARM64 Linux binaries but I won't hold my breath. I'm giving in and now researching what spec of Linux PC I should buy for my FPGA hardware work"  
[X Link](https://x.com/satnam6502/status/1953128318439703036) [@satnam6502](/creator/x/satnam6502) 2025-08-06T16:17Z 20.2K followers, 5682 engagements


"The two-sorter block is coming along well built with Lava combinators for a 7-series Xilinx FPGA. Next step: implement layout combinators to produce a compact efficient layout. After that: the full butterfly. A productive CalTrain trip"  
[X Link](https://x.com/satnam6502/status/1965459542088757397) [@satnam6502](/creator/x/satnam6502) 2025-09-09T16:57Z 20.2K followers, 8393 engagements


"The two-sorter now has an explicitly specified placement on the 7-series Xilinx FPGA and is anchored to the bottom left of the chip. I chose to do some recomputation to get shorter wire lengths (two CARRY4 blocks intermediate XNORs replicated) and I spread the pipeline registers across two slices rather than packing them into one. Next: expand the layout control to the whole butterfly"  
[X Link](https://x.com/satnam6502/status/1967077979194093918) [@satnam6502](/creator/x/satnam6502) 2025-09-14T04:08Z 20.2K followers, 4715 engagements


"I did some more hacking to produce a totally floorplanned 64-input sorter circuit on a Xilinx XC7A200T FPGA on the LHS picture shown as a tight rectangular block on the RHS a close-up that shows the butterfly wiring pattern. Produced from a hardware DSL written in Haskell using dependent types and combinators for computing the layout"  
[X Link](https://x.com/satnam6502/status/1970630298229772378) [@satnam6502](/creator/x/satnam6502) 2025-09-23T23:24Z 20.2K followers, 10.6K engagements


"I have landed my dream job. Ive just accepted a position at Harmonic a Palo Alto startup applying AI to formal mathematical reasoning. Harmonics Aristotle formal reasoning model achieved Gold Medal level performance at this years International Mathematical Olympiad (IMO). I will work on exploring applications of Aristotle to the formal verification of hardware. This job is a perfect intersection of hardware design and verification functional programming formal methods and machine learning bringing together several threads of my career so far. The beauty of asking an AI to generate a proof for"  
[X Link](https://x.com/satnam6502/status/1972741467564318902) [@satnam6502](/creator/x/satnam6502) 2025-09-29T19:13Z 20.2K followers, 233.7K engagements


"For the hot pan vs. cold pan controversy I am on the side of the hot pan. Seared duck breast with a whisky soy sauce (Oban 14) on a bed of spring onions asparagus and sugar snap peas. I started with a dry Hestan titanium pan at 200C and seared the scored salt and pepper skin side of two breasts totaling 600g for XX minutes turning the heat down to medium-low as soon as I added the duck breasts to the pan. After XX minutes of cooking on the skin side (constantly removing the rendered fat) I cooked the flesh side for X minutes. After resting for about X minutes the internal temperature got to"  
[X Link](https://x.com/satnam6502/status/1974682618701787563) [@satnam6502](/creator/x/satnam6502) 2025-10-05T03:46Z 20.2K followers, 3026 engagements


"A picture John Hughes took of me giving my keynote talk Functional Programming for Hardware Design at #icfpsplash25. A few key quotes/messages: * I love programming languages not for what they do I love programming languages for what they are. * I am a functional programmer not because of the company I work for but because of the company I keep. * Abstractions can be powerful but we must know their limits. * "But this is total madness": SystemVerilog semantics. * It is because I have spent so much of my time doing low level coding and optimization that I appreciate the value of functional"  
[X Link](https://x.com/satnam6502/status/1977876924690219277) [@satnam6502](/creator/x/satnam6502) 2025-10-13T23:19Z 20.2K followers, 14.8K engagements


"The video recording of my ICFP 2025 keynote talk Functional Programming for Hardware Design is up on YouTube"  
[X Link](https://x.com/satnam6502/status/1978236482901991726) [@satnam6502](/creator/x/satnam6502) 2025-10-14T23:08Z 20.2K followers, 6949 engagements


"Do you have any questions you would like to ask our panelists on the free to attend webinar "How can AI Revolutionize Hardware Verification" on Monday XX October at 16:00-17:00 BST (11:00-12:00 ET 8AM Pacific) The panelists are Sean Safarpour (Executive Director R&D Synopsys USA) Prof. Adam Chlipala (Professor of Computer Science MIT USA) and Kanad Basu (Rensselaer Polytechnic Institute USA). Please either enter questions in the comments below or email me at satnam6502@gmail.com or DM. Thank you Registration link:"  
[X Link](https://x.com/satnam6502/status/1978972315800211577) [@satnam6502](/creator/x/satnam6502) 2025-10-16T23:52Z 20.2K followers, 1248 engagements