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@cneralp "For this case I have calculated the necessary output capacitance as stated in the datasheet of the PMIC. I had to consider DC bias effect since we chose small components in terms of footprint size"
X Link @cneralp 2025-10-14T20:10Z 3730 followers, XXX engagements

"@alplabai When I consider the DC bias effect the effective capacitance reduces from 10uF to 4.2uF which creates higher input ripple. I might need to improve this for the next revision. The maximum desired ripple for the input is 50mV"
X Link @cneralp 2025-10-14T21:54Z 3730 followers, XXX engagements

"The routing is done finally Now DRC and fine tuning 🚀⚡"
X Link @cneralp 2025-10-02T13:27Z 3730 followers, 16.7K engagements

"Also you have to pay attention to the thermal performance otherwise you might have heating problems on your PCB. I have found this one from Qorvo Inc. which is very suitable for our HDI module (E1M)"
X Link @cneralp 2025-10-11T11:04Z 3730 followers, XXX engagements

"Another important detail is the input ripple which is related to input voltage output voltage output current frequency and input capacitor"
X Link @cneralp 2025-10-14T20:10Z 3730 followers, XXX engagements

"Smallest yet powerful plug & play industrial AI camera is coming soon with Renesas Electronics V2N MPU and DEEPX M1 AI Accelerator using our E1M-X module. Stay tuned for more details"
X Link @cneralp 2025-09-27T17:30Z 3725 followers, 2920 engagements

"I like putting design details to the schematic. It helps to keep the information organized and available easily during debugging and development. This is our E1M-X Renesas-DeepX SoM's PMIC design @alplabai #pmic #schematic #design #hardware"
X Link @cneralp 2025-10-14T20:10Z 3730 followers, 5732 engagements

"Do you use similar PMICs on your designs You can get a lot of power rails from one chip with complex sequence diagrams. However it comes with its own challenges you need to have blind and buried VIAs to fanout the signals"
X Link @cneralp 2025-10-11T11:04Z 3730 followers, 6025 engagements